Senior NVLink Validation Architect & Test Lead

NVIDIA; Westford (MA); On-site; USD 184,000 - 357,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Validation Architect for NVLink in Westford, MA to lead architectural validation for next-gen chip interconnects, define requirements, and partner with research, architecture, software, and product teams to shepherd designs through the full lifecycle.

You will define modeling and testing requirements, drive testbench integration, develop functional models, and support firmware/software teams across model, emulation, and post-silicon environments.

Qualifications

• MS or PhD in EE, CS, or CE (or equivalent experience).
• 8+ years of experience in architecture, design, and verification.
• Experience with innovative ASIC design processes.
• C++ and scripting (Python, Makefile); SystemC modeling is a plus.
• Strong FW/SW debugging and IP model integration.
• Test plan development and execution experience.
• Multiple shipped projects; experience with processor and/or I/O architecture.
• Self-starter; able to work in a small, dynamic team.

Responsibilities

• Define architectural modeling and testing requirements for new NVLink features.
• Drive architectural testing requirements into lower level testbenches.
• Implement functional models and integrate into full-chip and multi-chip environments for validation and firmware/software development.
• Support and debug tests in model, emulation, and post-silicon environments.

Skills

C++

Python

SystemC modeling

Debugging FW/SW

Testplan development

Architectural knowledge

Self-starter

Education

MS/PhD in Electrical Engineering, Computer Science or Computer Engineering

Tools

Makefile

SystemC

Job description

NVIDIA is seeking a Senior Validation Architect for NVLink in Westford, MA to lead architectural validation for next-gen chip interconnects, define requirements, and partner with research, architecture, software, and product teams to shepherd designs through the full lifecycle.

You will define modeling and testing requirements, drive testbench integration, develop functional models, and support firmware/software teams across model, emulation, and post-silicon environments.