Senior NoC/SoC Design Engineer for AI ASICs (Hybrid)

Scubyt Inc; Mountain View (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Scubyt Inc. in Mountain View, CA, seeks a Senior ASIC / SoC NoC Design Engineer to architect and implement high-bandwidth Network-on-Chip IP for AI-focused SoCs.

This onsite/hybrid role requires deep hands-on experience in RTL, microarchitecture, and system integration. You will drive synthesis, timing, CDC, lint, and PPA closure, collaborate across architecture, verification, physical design, and SOC teams, and contribute to design reviews while developing Python-based automation to boost

Qualifications

• 8+ years of experience delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.

Responsibilities

• Design NoC IP for AI SoCs with high bandwidth and performance.
• Define microarchitecture specifications and translate to RTL.
• Develop RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC, lint, and PPA closure.
• Analyze and optimize designs for power, performance, and area.
• Support SoC integration and system-level design activities.
• Participate in post-silicon debug and issue resolution.
• Collaborate with architecture, verification, physical design, and SoC teams.
• Develop Python scripts and automation tools to improve design productivity.
• Participate in design reviews and contribute to decisions.

Skills

RTL design

Synthesis

NoC/Network-on-Chip

Verilog

SystemVerilog

Microarchitecture

CDC

Lint

Timing

PPA optimization

SoC integration

Post-Silicon Debug

Tools

Python scripting (automation)

Job description

Scubyt Inc. in Mountain View, CA, seeks a Senior ASIC / SoC NoC Design Engineer to architect and implement high-bandwidth Network-on-Chip IP for AI-focused SoCs.

This onsite/hybrid role requires deep hands-on experience in RTL, microarchitecture, and system integration. You will drive synthesis, timing, CDC, lint, and PPA closure, collaborate across architecture, verification, physical design, and SOC teams, and contribute to design reviews while developing Python-based automation to boost