Senior ASIC / SoC Network-on-Chip Design Engineer

Themesoft Inc; Mountain View (MO); Hybrid; USD 180,000 - 240,000; Full time

Job summary

The Mountain View team at Themesoft Inc is seeking a senior ASIC/SoC design engineer to design high-performance NoC IP for AI SoCs. You will collaborate across architecture, verification, physical design, and integration teams to deliver synthesizeable RTL.

Candidates should have extensive experience with Verilog/SystemVerilog, timing constraints, CDC/Lint, Synthesis, and Python scripting, plus a track record of NoC/interconnect and post-silicon debug in complex SoCs.

Qualifications

• 8+ years delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.

Responsibilities

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Skills

ASIC design

NoC

RTL design

SystemVerilog

Python scripting

SoC integration

Job description

Job Id : OOJ - 27183

Posted Date : 09/18/2026

Experience : -

Job Type : Full Time

Location : Mountain View, CA

Overview :

Location: Mountain View CA (onsite - Hybrid)

Job Type: FullTime.

Responsibilities

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Qualifications

• 8+ years delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.

Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python