Senior ASIC / SoC Network-on-Chip (NoC) Design Engineer

Scubyt Inc; Mountain View (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Scubyt Inc. in Mountain View, CA, seeks a Senior ASIC / SoC NoC Design Engineer to architect and implement high-bandwidth Network-on-Chip IP for AI-focused SoCs.

This onsite/hybrid role requires deep hands-on experience in RTL, microarchitecture, and system integration. You will drive synthesis, timing, CDC, lint, and PPA closure, collaborate across architecture, verification, physical design, and SOC teams, and contribute to design reviews while developing Python-based automation to boost

Qualifications

• 8+ years of experience delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.

Responsibilities

• Design NoC IP for AI SoCs with high bandwidth and performance.
• Define microarchitecture specifications and translate to RTL.
• Develop RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC, lint, and PPA closure.
• Analyze and optimize designs for power, performance, and area.
• Support SoC integration and system-level design activities.
• Participate in post-silicon debug and issue resolution.
• Collaborate with architecture, verification, physical design, and SoC teams.
• Develop Python scripts and automation tools to improve design productivity.
• Participate in design reviews and contribute to decisions.

Skills

RTL design

Synthesis

NoC/Network-on-Chip

Verilog

SystemVerilog

Microarchitecture

CDC

Lint

Timing

PPA optimization

SoC integration

Post-Silicon Debug

Tools

Python scripting (automation)

Job description

Job Role: Senior ASIC / SoC Network-on-Chip (NoC) Design Engineer

Location: Mountain View, CA

Work Model: Onsite / Hybrid

Experience: 8+ years

Employment Type: Contract/Full-Time

POSITION OVERVIEW:

• We are seeking a highly experienced Senior ASIC / SoC Network-on-Chip (NoC) Design Engineer to design high-performance, high-bandwidth NoC IP for advanced AI SoCs.
• The ideal candidate will have strong hands-on experience in ASIC/SoC design, RTL development, microarchitecture, NoC/interconnect design, synthesis, timing, CDC, lint, PPA optimization, and SoC integration.

RESPONSIBILITIES:

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and translate architectural requirements into synthesizable RTL.
• Develop high-quality RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC, lint, and PPA closure.
• Analyze and optimize designs for power, performance, and area (PPA).
• Support SoC integration and system-level design activities.
• Participate in post-silicon debug and issue resolution.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts and automation tools to improve design productivity and engineering efficiency.
• Participate in design reviews and contribute to microarchitecture and implementation decisions.

REQUIRED QUALIFICATIONS:

• 8+ years of experience delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.

STRONG EXPERIENCE WITH:

• RTL design
• Synthesis
• Experience with high-throughput and low-latency designs.
• Experience with SoC integration.
• Experience with post-silicon debug.
• Strong Python scripting and design-automation experience.

KEY SKILLS:

ASIC | SoC | NoC | Network-on-Chip | RTL | Verilog | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python | SoC Integration | Post-Silicon Debug