Senior ASIC Design Engineer for AI Accelerators

Oho Group; San Jose (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Oho Group in the San Francisco Bay Area is seeking a Lead ASIC Design Engineer with 10+ years of ASIC/SoC experience to own RTL design and microarchitecture for high-performance AI accelerator solutions.

You will collaborate with verification, architecture, software and system teams, work on PCIe/CXL/UCIe interconnects and memory systems, and contribute across the silicon development lifecycle from early stage development.

Qualifications

• 10+ years of ASIC/SoC design experience with hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with PCIe, CXL or UCIe interconnect technologies.

Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and protocols.
• Define and review microarchitectural specs and translate to synthesizable RTL.
• Collaborate with architecture, verification, software and system teams throughout silicon development cycle.

Skills

RTL design

Microarchitecture

SoC design

Interconnects

PCIe / CXL / UCIe

GPU/AI accelerator experience

Education

BS, MS or PhD in Electrical Engineering / Computer Engineering / CS

Tools

PCIe

CXL

UCIe

HBM

Job description

Oho Group in the San Francisco Bay Area is seeking a Lead ASIC Design Engineer with 10+ years of ASIC/SoC experience to own RTL design and microarchitecture for high-performance AI accelerator solutions.

You will collaborate with verification, architecture, software and system teams, work on PCIe/CXL/UCIe interconnects and memory systems, and contribute across the silicon development lifecycle from early stage development.