Senior ASIC Design Lead for AI Data Center

Netpreme; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health, dental, vision

Equity grant

401(k) match

Life & disability insurance

Wellness stipend

Daily lunch stipend

EV charging on-site

Visa sponsorship

Job summary

Netpreme is seeking experienced Senior ASIC Designers to join our Silicon Design Team and lead RTL design of IPs, subsystems, and SOCs for our silicon roadmap. You will define microarchitecture specifications and design methodologies, while conducting design reviews to ensure best practices.

This early-stage startup focuses on AI/DataCenter applications, memory acceleration, and collaboration across architecture, verification, physical design, firmware, DFT, and post-silicon teams to deliver

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5+ years of ASIC/SOC digital design experience
• Excellent leadership, communication, team building and stakeholder management skills.
• Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
• Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).

Responsibilities

• RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.
• Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
• Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
• Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
• Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

STA/timing closure

Physical design

Verification methodologies

Lead cross-functional teams

PPA optimization

Interconnect/Memory integration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Job description

Netpreme is seeking experienced Senior ASIC Designers to join our Silicon Design Team and lead RTL design of IPs, subsystems, and SOCs for our silicon roadmap. You will define microarchitecture specifications and design methodologies, while conducting design reviews to ensure best practices.

This early-stage startup focuses on AI/DataCenter applications, memory acceleration, and collaboration across architecture, verification, physical design, firmware, DFT, and post-silicon teams to deliver