Senior NoC/SoC ASIC Design Engineer - Verilog & Python

Wipro Technologies; San Diego (CA); On-site; USD 60,000 - 140,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Disability insurance

Paid time off

Leave options

Job summary

Wipro Limited in Mountain View, California, is seeking an experienced Senior ASIC / SoC NoC Design Engineer or Senior ASIC Design Engineer to drive high-performance NoC IP within AI SoCs. The role requires hands-on RTL design, microarchitecture, and strong collaboration across architecting and verification teams.

The position emphasizes Synthesis, timing, CDC/Lint, PPA trade-offs, and post-silicon support, with Python scripting to automate design flows.

Qualifications

• 8+ years delivering ASIC/SoC IP designs.
• 6+ years digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.

Responsibilities

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Skills

ASIC/SoC IP design

Verilog/SystemVerilog

Python scripting

NoC / interconnect

Post-silicon debug

Tools

Synthesis tools

Job description

Wipro Limited in Mountain View, California, is seeking an experienced Senior ASIC / SoC NoC Design Engineer or Senior ASIC Design Engineer to drive high-performance NoC IP within AI SoCs. The role requires hands-on RTL design, microarchitecture, and strong collaboration across architecting and verification teams.

The position emphasizes Synthesis, timing, CDC/Lint, PPA trade-offs, and post-silicon support, with Python scripting to automate design flows.