Senior NAND Design Engineer - Core & AI-Driven EDA

Micron Technology, Inc.; San Jose (CA); On-site; USD 120,000 - 204,000; Full time

Job summary

Micron Technology, Inc. seeks a Senior/Staff Design Engineer for the NVE Design Engineering Core group to develop memory core circuits and advanced array architectures. You will collaborate with Firmware, Analog, and Validation teams to optimize NAND read/program/erase algorithms and power.

You’ll drive simulations, layout, and Python automation across full-chip integration. The role requires strong fundamentals in semiconductor physics, 4+ years NAND design, and expertise in Python, Cadence,

Qualifications

• MS in electrical engineering required.
• 4+ years of NAND design experience.
• Strong fundamentals in semiconductor physics and analog/mixed-signal design.
• Proficient in Python and scripting.
• Excellent teamwork and English communication.

Responsibilities

• Develop array waveforms with timing and biasing for NAND read, program, and erase.
• Collaborate with Firmware, Analog, and Design validation teams.
• Plan wordline and bitline path architecture to meet area, performance and power specs.
• Perform die size cost/benefits analysis and evaluate NAND power consumption.
• Create Xpath, Ypath and Array schematics; integrate core schematics into full-chip; perform SPICE simulations and oversee layout.
• Develop Python-based automation and AI-assisted design utilities.
• Review and generate user documentation.

Skills

NAND design

Python

Mixed-signal design

Circuit debugging

Team collaboration

English communication

Education

MS in Electrical Engineering

Tools

Cadence design

HSPICE

Verilog

Spice simulations

CSV/JSON/SQLite

Git/version control

Job description

Micron Technology, Inc. seeks a Senior/Staff Design Engineer for the NVE Design Engineering Core group to develop memory core circuits and advanced array architectures. You will collaborate with Firmware, Analog, and Validation teams to optimize NAND read/program/erase algorithms and power.

You’ll drive simulations, layout, and Python automation across full-chip integration. The role requires strong fundamentals in semiconductor physics, 4+ years NAND design, and expertise in Python, Cadence,