NAND Design Automation Architect | AI-Driven Flows

Anysilicon; San Jose (CA); Hybrid; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

Micron Technology is seeking a Staff/Principal Design Engineer to lead NAND circuit development, focusing on design automation and enablement. You will drive core Xpath/Ypath/Array design, integrate schematics into full chip designs, and validate performance through simulations.

The role requires a strong background in analog/mixed-signal design and 8+ years in NAND design, with expertise in Cadence, HSPICE, Verilog, and UNIX environments. Collaboration across teams is essential.

Qualifikationen

• MS in Electrical Engineering required.
• PhD preferred.
• 8+ years NAND design experience.
• Strong fundamentals in semiconductor physics.
• Experience in circuit verification, optimization, and layout planning.
• Proficiency with design tools (Cadence, HSPICE, Verilog).

Aufgaben

• Lead NAND circuit development through design automation and enablement.
• Implement core Xpath, Ypath, and Array design during project execution.
• Validate design performance via block and chip-level simulations.
• Design and validate analog and mixed-signal circuits (charge pumps, op amps, DACs, ADCs).
• Serve as technical authority solving complex modeling and simulation issues.
• Develop AI/LLM-assisted flows for circuit design and automated checks.
• Collaborate with multi-functional teams to ensure manufacturability and testability.
• Reduce cycle time by integrating automation with project execution.

Kenntnisse

Circuit design verification flows

Analog/mixed-signal circuit design

Python for engineering automation

Verilog

HSPICE

UNIX experience

Ausbildung

MS in Electrical Engineering

PhD preferred

Tools

Cadence design tools

HSPICE

Verilog

UNIX environment

Jobbeschreibung

Micron Technology is seeking a Staff/Principal Design Engineer to lead NAND circuit development, focusing on design automation and enablement. You will drive core Xpath/Ypath/Array design, integrate schematics into full chip designs, and validate performance through simulations.

The role requires a strong background in analog/mixed-signal design and 8+ years in NAND design, with expertise in Cadence, HSPICE, Verilog, and UNIX environments. Collaboration across teams is essential.