Senior MXS Verification engineer

Retym Israel Ltd; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

A cutting-edge technology startup is seeking a Sr Mixed Signal Verification Engineer to develop verification strategies for high-speed communication technology. Candidates should possess over 10 years of experience in verification, expertise in Verilog/SystemVerilog coding, and proven skills in behavioral modeling. The role emphasizes collaboration in a team environment and excellent communication skills. This opportunity is based in Austin, Texas and offers an exciting work environment.

Qualifications

• 10+ years of experience in verification.
• Experience in Behavioral Modeling for digital verification.
• Familiarity with verification methodologies and tools.

Responsibilities

• Develop verification strategies for mixed-signal designs.
• Create behavioral models according to specifications.
• Write, execute, and debug testbenches for mixed-signal blocks.

Skills

Behavioral Modeling of Analog Design

Verilog/SystemVerilog Coding

UVM Methodologies

Debugging Testbenches

Collaboration in Team Environment

Strong Communication Skills

Tools

Virtuoso Schematics

AMS Tools

Synopsys Tools

Cadence Tools

Job description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.

Requirements

Key Responsibilities:

• Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
• Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
• Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
• Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
• Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.

Minimum Qualifications

• 10+ years of experience
• Experience in Behavioural Modelling (BM) of Analog design for digital verification
• Experience in Verilog/SystemVerilog coding
• Experience in Virtuoso Schematics toolsBasic knowledge in Analog design

Preferred Qualifications

• Experience in UVM
• Experience in both Synopsys and Cadence tools is an advantage

Additional Skills

• Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
• Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
• Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.