Mixed Signal Verification Engineer

Oho Group; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Massive chances for progression

Real end-to-end projects

Exciting project ownership

Job summary

Oho Group is seeking a Mixed Signal Engineer in Austin, Texas, to lead verification for digital and analog designs. This role involves developing verification strategies and collaborating with analog design teams. With a requirement of 5+ years of experience and proficiency in Verilog/SystemVerilog, this position offers an excellent opportunity at a rapidly growing startup focused on innovating AI connectivity. Enjoy significant progression opportunities while working on cutting-edge technology.

Qualifications

• 5+ years of relevant industry experience.
• Experience in behavioral modeling of analog designs for digital verification.
• Proficiency in Verilog/SystemVerilog.

Responsibilities

• Develop verification strategies for mixed-signal designs using UVM methodologies.
• Contribute towards behavioral models for analog blocks in collaboration with analog design teams.
• Write, execute, and debug testbenches using SystemVerilog for mixed-signal designs.

Skills

Behavioral modeling of analog designs for digital verification

Proficiency in Verilog/SystemVerilog

Experience with schematic design tools

Basic understanding of analog design principles

Verification strategies for mixed-signal designs

Job description

Mixed Signal Engineer | AI Startup | Austin, Texas

A leading semiconductor startup in Austin is looking for a Mixed Signal Verification Engineer to spearhead its growing team. Recently launching out of stealth with significant investment, this is the perfect time to get on board!

What's in it for you:

• Real end-to-end projects
• Massive chances for progression at a well-backed and fast-growing startup
• Contribute to next-level technology that is changing the game of AI connectivity

What you'll be doing:

• Develop verification strategies for digital and analog (mixed-signal) designs using UVM methodologies based on specifications.
• Contribute towards behavioral models for analog blocks in collaboration with analog design teams.
• Write, execute, and debug testbenches using UVM methodology and SystemVerilog for mixed-signal designs.
• Conduct and troubleshoot simulations at unit, subsystem, and full-system levels for mixed-signal designs.

What you need:

• 5+ years of relevant industry experience
• Experience in behavioral modeling of analog designs for digital verification
• Proficiency in Verilog/SystemVerilog
• Experience with schematic design tools (e.g., industry-standard platforms)
• Basic understanding of analog design principles

Please note that this role will require 5 days onsite. If you're looking for ownership in an exciting project, click apply now!