Senior Multicore DSP & Embedded Systems Engineer

Teradar; Boston (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

Teradar is hiring a DSP Software Developer to architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across cores and optimizing data movement over a network-on-chip.

You will work close to the metal, scaling workloads across many cores, and optimizing hot inner loops on each core. Experience with SIMD, VLIW, and pre-silicon validation is essential for delivering high-performance radar pipelines.

Qualifications

• Extensive experience in multicore embedded software for SoCs.
• Experience with shared/distributed memory and DMA-driven data movement.
• Knowledge of bare-metal or RTOS programming, boot flow, memory maps, and real-time scheduling.
• Strong understanding of computer architecture and micro-architecture fundamentals.
• Proficiency in C/C++ with SIMD and VLIW intrinsics.
• Familiarity with radar signal processing concepts (FMCW, FFT, CFAR, MIMO).

Responsibilities

• Architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across cores.
• Design data and task decomposition strategies to balance compute load and minimize inter-core communication.
• Manage a multi-level memory hierarchy and orchestrate DMA transfers to sustain high throughput.
• Develop and optimize per-core radar kernels using SIMD, VLIW, and intrinsics.
• Build pre-silicon validation platforms for early multicore software development.
• Profile pipelines to identify bottlenecks and optimize partitioning, scheduling, and data layout.

Skills

Multicore software

Memory hierarchy

DMA data movement

Bare-metal/RTOS

C/C++

SIMD/VLIW

Radar signal processing

Pre-silicon validation

Tools

Virtual prototypes

SIMD intrinsics

VLIW programming

Job description

Teradar is hiring a DSP Software Developer to architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across cores and optimizing data movement over a network-on-chip.

You will work close to the metal, scaling workloads across many cores, and optimizing hot inner loops on each core. Experience with SIMD, VLIW, and pre-silicon validation is essential for delivering high-performance radar pipelines.