Senior DSP & Embedded Systems Engineer - Heterogeneous SoC

Teradar; Boston (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

Teradar is hiring a DSP Software Developer to architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across cores and optimizing data movement over a network-on-chip.

You will work close to the metal, scaling workloads across many cores, and optimizing hot inner loops on each core. Experience with SIMD, VLIW, and pre-silicon validation is essential for delivering high-performance radar pipelines.

Qualifications

• Extensive experience in multicore embedded software for SoCs.
• Experience with shared/distributed memory and DMA-driven data movement.
• Knowledge of bare-metal or RTOS programming, boot flow, memory maps, and real-time scheduling.
• Strong understanding of computer architecture and micro-architecture fundamentals.
• Proficiency in C/C++ with SIMD and VLIW intrinsics.
• Familiarity with radar signal processing concepts (FMCW, FFT, CFAR, MIMO).

Responsibilities

• Architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across cores.
• Design data and task decomposition strategies to balance compute load and minimize inter-core communication.
• Manage a multi-level memory hierarchy and orchestrate DMA transfers to sustain high throughput.
• Develop and optimize per-core radar kernels using SIMD, VLIW, and intrinsics.
• Build pre-silicon validation platforms for early multicore software development.
• Profile pipelines to identify bottlenecks and optimize partitioning, scheduling, and data layout.

Skills

Multicore software

Memory hierarchy

DMA data movement

Bare-metal/RTOS

C/C++

SIMD/VLIW

Radar signal processing

Pre-silicon validation

Tools

Virtual prototypes

SIMD intrinsics

VLIW programming

Job description

At Teradar, we are pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high-resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond.

We are looking to hire a DSP Software Developer: someone capable of partitioning real-time signal processing pipelines across heterogeneous DSP cores, squeezing every cycle out of shared-memory hierarchies, and orchestrating data movement over a Network-on-Chip.

You’ll work close to the metal on both fronts: scaling workloads across many cores and optimizing the hot inner loops on each one.

Responsibilities

• Architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across multiple cores connected by a network-on-chip.
• Design data and task decomposition strategies that balance compute load, minimize inter-core communication, and exploit pipeline, data, and functional parallelism across radar processing stages.
• Manage a multi-level memory hierarchy (core-local, cluster-shared, and SoC-global) - placing buffers, sizing working sets, and orchestrating DMA transfers to sustain high memory throughput and keep cores fed with radar data cubes while hiding stalls behind useful work.
• Develop and optimize per-core radar kernels (FFTs, filters, matrix operations, CFAR variants, MIMO processing) using SIMD, VLIW, fractional arithmetic, and intrinsics.
• Build, use, and maintain pre-silicon validation platforms such as virtual prototypes for early multicore software development, performance projection, and testing.
• Profile end-to-end radar pipelines across cores - identifying load imbalance, NoC contention, memory bandwidth bottlenecks, and synchronization overhead - and iterate on partitioning, scheduling, and data layout to optimize performance, power, and area trade-offs.

Skills & Experience

• Strong experience developing multicore embedded software on an SoC, including workload partitioning, scheduling, and load balancing across cores.
• Hands-on experience managing shared and distributed memory across a multi-level memory hierarchy, including explicit DMA-driven data movement, double/multi-buffering, and techniques for sustaining high memory throughput under real-time constraints.
• Working knowledge of bare-metal programming and/or real-time operating systems, including boot flow, linker scripts, memory maps, interrupt and exception handling, and real-time task scheduling.
• Solid understanding of computer architecture and micro-architecture fundamentals.
• Proficiency in C/C++ along with SIMD and VLIW programming models, intrinsics, and fractional arithmetic applied to radar or DSP kernels.
• Familiarity with radar signal processing concepts - FMCW radar, Range/Doppler/Angle estimation, FFTs, CFAR detection, beamforming, MIMO, and tracking, and the data-flow and bandwidth characteristics they impose on the processing pipeline.
• Exposure to virtual prototypes or pre-silicon validation platforms.
• Ability to analyze and resolve performance bottlenecks spanning compute, memory bandwidth, NoC, and synchronization, and to optimize for PPA across the full multicore radar pipeline.