Senior MRAM Synthesis & P&R Engineer

Numem Inc.; Mesa (AZ); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Numem Inc. in Mesa, AZ is seeking an experienced Synthesis & Place & Route (P&R) Design Engineer to lead RTL-to-GDSII for embedded MRAM controllers and MRAM memory subsystems. This on-site role focuses on PPA balance across advanced nodes and tight timing constraints.

The ideal candidate brings 7+ years in physical design, with strong proficiency in Synthesis, DFT, P&R tools, and TCL/Python scripting, and a track record of sign-off through full flow from RTL to tape-out.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of hands-on physical design experience from logical synthesis to GDSII sign-off.
• Tool proficiency in Synthesis & DFT: Synopsys Design Compiler or Cadence Genus; Tessent / Synopsys DFT.
• Tool proficiency in P&R: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
• Tool proficiency in STA & Power Integrity: Synopsys PrimeTime / RedHawk or Cadence Tempus / Voltus.
• Tool proficiency in Physical Verification: Calibre (DRC/LVS).
• Advanced Tcl and Python scripting for flows.

Responsibilities

• Lead synthesis and DFT insertion for complex MRAM memory controllers, built-in self-repair logic, and ECC engines for MRAM reliability.
• Develop and maintain MCMM timing constraints (SDC) for high-speed read/write interfaces across temperature and voltage ranges.
• Optimize synthesized netlists to leverage MRAM's non-volatile nature for instant-on and ultra-low leakage power targets.
• Collaborate with layout teams to plan floor planning, macro placement, reset and timing constraints, and BEOL rule sets.
• Execute macro placement and floor planning for dense MRAM arrays with BEOL constraints from MTJ integration.
• Construct robust PDN capable of handling transient surges and high write-peak currents during switching; manage UPF/CPF power-domain crossing.

Skills

Synthesis

DFT insertion

Timing constraints

Floor planning

Clock tree synthesis

Power integrity

CTS

Education

B.S./M.S. in Electrical Engineering

Tools

Synopsys Design Compiler

Cadence Genus

Fusion Compiler

Tessent

Calibre

Tempus

Voltus

ICC2

Innovus

Job description

Numem Inc. in Mesa, AZ is seeking an experienced Synthesis & Place & Route (P&R) Design Engineer to lead RTL-to-GDSII for embedded MRAM controllers and MRAM memory subsystems. This on-site role focuses on PPA balance across advanced nodes and tight timing constraints.

The ideal candidate brings 7+ years in physical design, with strong proficiency in Synthesis, DFT, P&R tools, and TCL/Python scripting, and a track record of sign-off through full flow from RTL to tape-out.