Senior SRAM/ROM Memory Circuit Design Engineer

NXP Semiconductors; Austin (TX); On-site; USD 130,000 - 170,000; Full time

Job summary

NXP Semiconductors in Austin is seeking an experienced memory circuit design engineer to advance our SRAM and ROM memory compiler designs. You will collaborate with global memory teams to meet performance, power, and area targets, and to integrate designs into verification flows.

The role requires 8+ years in SRAM memory design, with 5nm+ process exposure, strong Cadence Virtuoso skills, and scripting ability in Perl/Tcl/Python. A Master’s is preferred and office-based collaboration is expected.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 8+ years in SRAM memory circuit design, with 5nm+ process experience.
• Strong familiarity with Cadence Virtuoso and other EDA tools.
• Scripting skills in Perl, Tcl, or Python required.
• Analytical, creative problem-solving abilities.

Responsibilities

• Implement CMOS memory circuit designs to meet performance, power, and area targets.
• Generate, execute, and evaluate simulation data and test benches against benchmarks.
• Collaborate with layout teams to optimize area and performance of leaf cells.
• Work with CAD teams to integrate designs into characterization and verification flows.
• Coordinate with frontend modeling teams to ensure design fidelity with behavioral models.
• Leverage GenAI tools to improve design methodologies.

Skills

Scripting languages

Analytical thinking

Creative mindset

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree preferred

Tools

Cadence Virtuoso

EDA tools

Job description

NXP Semiconductors in Austin is seeking an experienced memory circuit design engineer to advance our SRAM and ROM memory compiler designs. You will collaborate with global memory teams to meet performance, power, and area targets, and to integrate designs into verification flows.

The role requires 8+ years in SRAM memory design, with 5nm+ process exposure, strong Cadence Virtuoso skills, and scripting ability in Perl/Tcl/Python. A Master’s is preferred and office-based collaboration is expected.