Senior Lead Memory Circuit Design Engineer

W3Global; Sunnyvale (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

W3Global is seeking a Senior Lead Memory Circuit Design Engineer to drive end-to-end memory subsystem design for advanced mixed-signal SoCs. You will lead architecture, design, verification, and tapeout, collaborating with Analog, Digital, Verification, and Layout teams.

Responsibilities include designing memory arrays, sense amplifiers, references, and decoders; performing SPICE simulations and reliability analyses; reviewing timing and signoff; and mentoring engineers while guiding

Qualifications

• 15+ years of memory circuit design experience, including SRAM and NVM.
• Multiple successful tapeouts with subsystem ownership.

Responsibilities

• Own memory architecture, circuit design, verification, signoff, and tapeout.
• Design/optimize memory arrays, sense amplifiers, references, read/write circuits, decoders, and datapaths.
• Perform SPICE simulations, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability analysis.
• Review chip-level timing issues, margins, waveforms, and signoff results.
• Partner with Layout on floorplanning, parasitics, EM/IR, density, antenna, signoff.
• Mentor engineers and lead cross-functional execution.

Skills

Memory architecture

Leadership

Mixed-signal design

Mentoring

Education

BSEE/MSEE/PhD or equivalent

Tools

Cadence/Synopsys

HSPICE

Spectre

PrimeSim

Job description

Senior Lead Memory Circuit Design Engineer - Mixed-Signal / NVM

Location:

Mesa, AZ (preferred; CA candidates considered)

Role

Lead end-to-end memory subsystem design from architecture through tapeout for advanced mixed-signal SoCs, collaborating with Analog, Digital, Verification, and Layout teams.

Key Responsibilities

• Own memory architecture, circuit design, verification, signoff, and tapeout.
• Design/optimize memory arrays, sense amplifiers, references, read/write circuits, decoders, and datapaths.
• Perform SPICE simulations, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability analysis.
• Review chip-level timing issues, margins, waveforms, and signoff results.
• Partner with Layout on floorplanning, parasitics, EM/IR, density, antenna, and signoff.
• Mentor engineers and lead cross-functional execution.

Required Qualifications

• BSEE/MSEE/PhD or equivalent.
• 15+ years of memory circuit design experience, including SRAM and NVM.
• Multiple successful tapeouts with subsystem/block ownership.
• Strong mixed-signal, sense amplifier, reference generation, and memory architecture expertise.
• Experience with Cadence/Synopsys and SPICE tools such as HSPICE, Spectre, or PrimeSim.
• Strong leadership and mentoring skills.

Preferred

• MRAM/RRAM or other resistive/NVM experience.
• Silicon characterization and post-silicon debug.
• Crosspoint-style memory architectures.
• EM/IR, ESD, latch-up, and reliability signoff experience.