Senior Mixed-Signal Verification Engineer — SoC Focus

Arago; Paris (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Stock options

Healthcare coverage

Pension contributions

Professional development

Job summary

Arago is hiring a Senior Mixed-Signal Verification Engineer to lead the methodology and execution of mixed-signal verification for digital-to-analog interfaces on Arago’s SoCs. You will collaborate across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

The role requires hands-on ASIC/SoC verification experience, proficiency in SystemVerilog and UVM, and strong debugging and scripting skills.

Qualifications

• Strong hands-on experience in ASIC or SoC verification.
• Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.
• Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.
• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
• Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts.
• Strong debugging skills, spanning RTL, models, clocks, resets, configuration and analog behavior.
• Experience with scripting and automation, preferably Python, Tcl, shell, or similar.
• Language: English at a proficient level.

Responsibilities

• Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.
• Build and maintain verification environments at block, subsystem, and SoC level.
• Develop tests, assertions, checkers, scoreboards, and functional coverage.
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
• Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.
• Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.

Skills

ASIC/SoC verification

Mixed-signal verification

SystemVerilog + UVM

Verification environments

Debugging

Digital design fundamentals

Scripting in Python/Tcl

English proficiency

Job description

Arago is hiring a Senior Mixed-Signal Verification Engineer to lead the methodology and execution of mixed-signal verification for digital-to-analog interfaces on Arago’s SoCs. You will collaborate across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

The role requires hands-on ASIC/SoC verification experience, proficiency in SystemVerilog and UVM, and strong debugging and scripting skills.