Mixed-Signal Verification Engineer for Automotive ICs

allegromicro; Manchester (NH); On-site; USD 90,000 - 120,000; Full time

Job summary

Allegro MicroSystems is seeking a driven Mixed-Signal Design Verification Engineer to join our electronics team. You will develop and execute testbenches, verify chip-level interactions between analog front-ends and digital logic, and ensure first-pass silicon success.

You will work with senior leads to validate power sequences, register maps, and ECU-level testcases, while collaborating across design teams to close coverage and drive tapeout readiness in a global engineering environment.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 1–3 years of industry or academic experience in mixed-signal verification or IC design.
• Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).
• Understanding of Verilog, SystemVerilog and Verilog-A/AMS basics.
• Solid grasp of analog blocks (amplifiers, bandgaps, LDOs, ADCs) and digital logic.

Responsibilities

• Run and debug top-level mixed-signal simulations to verify chip-level interactions.
• Develop and maintain behavioral models and testbenches using Verilog, SystemVerilog, Verilog-AMS/RNM.
• Verify power-up/power-down sequences, reset circuits, and temperature corners.
• Validate register maps and EEPROM configurations against design specs.
• Track verification bugs using GitLab and support tapeout readiness.
• Collaborate with Analog/Digital/Systems teams to review coverage metrics in Jama Connect.

Skills

Verilog/SystemVerilog

Problem solving

Communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence Virtuoso

AMS Designer

ADE Explorer/Assembler

Job description

Allegro MicroSystems is seeking a driven Mixed-Signal Design Verification Engineer to join our electronics team. You will develop and execute testbenches, verify chip-level interactions between analog front-ends and digital logic, and ensure first-pass silicon success.

You will work with senior leads to validate power sequences, register maps, and ECU-level testcases, while collaborating across design teams to close coverage and drive tapeout readiness in a global engineering environment.