Principal Engineer, ASIC Verification

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Ayar Labs is seeking a Principal Design Verification Engineer to lead verification strategy for its next-generation silicon photonic chip. You will architect scalable UVM environments, set standards, and drive high-quality tape-out while mentoring a team of engineers.

Responsibilities include defining verification plans with Architects, debugging RTL/firmware issues, and building regression automation to close coverage. Collaboration with cross-functional teams is essential for success.

Qualifications

• MS in Electrical Engineering, Computer Engineering, or related field
• 12+ years of ASIC/SoC verification experience
• Expert-level SystemVerilog and UVM
• Proven track record building verification environments from scratch
• Deep knowledge of PCIe, ARM MCU, AMBA/AXI, UCIe
• Scripting languages: Python, Perl, Tcl, or Shell
• Functional coverage groups and 100% logic verification closure

Responsibilities

• Architect modular, reusable UVM testbenches for complex IP blocks.
• Set verification standards, guidelines, and coverage metrics.
• Collaborate with Architects and RTL Designers on verification plans.
• Lead debugging across RTL, firmware, and verification environments.
• Mentor engineers and conduct code reviews.
• Develop scripts/infrastructure for regression testing and coverage closure.

Skills

SystemVerilog

UVM

Mentoring

Regression testing

Clock-domain verification

AMS verification

SerDes interfaces

HBM interfaces

SVA

Python scripting

Education

MS in Electrical/Computer Engineering

Tools

Emulation platforms

AMS verification tools

C/C++ modeling

Job description

Ayar Labs is seeking a Principal Design Verification Engineer to lead the verification strategy for its next-generation silicon photonic chip. This role involves architecting scalable verification environments and driving high-quality silicon from concept to tape-out, focusing on complex system-level challenges and mentoring a team of engineers.

Responsibilities:

• Architect modular, reusable, and scalable UVM testbench architectures for complex IP blocks and subsystems.
• Set standards for verification methodologies, coding guidelines, and coverage metrics.
• Collaborate with Architects and RTL Designers to define verification plans and identify architectural bottlenecks.
• Lead debugging efforts to root-cause hardware bugs across RTL, firmware, and verification environments.
• Mentor engineers, conduct code reviews, and promote engineering excellence.
• Develop scripts and infrastructure for automating regression testing, performance analysis, and coverage closure.

Qualifications:

• MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of ASIC/SoC verification experience.
• Expert-level proficiency in SystemVerilog and UVM.
• Proven track record of building verification environments from scratch.
• Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe).
• Strong proficiency in scripting languages (Python, Perl, Tcl, or Shell).
• Experience defining functional coverage groups and achieving 100% logic verification closure.

Skills:

• Formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions).
• Hands-on experience with hardware emulation platforms.
• Familiarity with RISC-V or ARM architecture and coherency protocols.
• Experience in Analog/Mixed-Signal (AMS) verification.
• C/C++ or SystemC modeling for reference models.
• Verification of digital designs with multiple clock domains and clock dividers.
• Verification of SerDes IP block interfaces in complex SoC environments.
• Verification of HBM memory interfaces (PHY and controller).Experience with formal model equivalence checking tools.