Mixed-Signal Verification Engineer — Drive First-Pass Silicon

Allegro MicroSystems, LLC; Manchester (NH); On-site; USD 90,000 - 120,000; Full time

Job summary

Allegro MicroSystems, LLC is seeking a Mixed-Signal Design Verification Engineer to develop and execute top-level verification testbenches for automotive and industrial ICs. You will bridge analog blocks and digital control, running functional simulations across power sequencing and test cases to ensure first-pass silicon success.

You will collaborate with Analog, Digital Design, and Systems Engineering to review coverage metrics and support testcase closure, using Cadence AMS Designer,

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related discipline.
• 1–3 years in mixed-signal verification or IC design (industry or academia).
• Familiarity with Cadence EDA tools and HDL languages like Verilog/SystemVerilog.

Responsibilities

• Run and debug top-level mixed-signal simulations with Cadence tools.
• Verify power-up/down sequences, POR/POK/UVLO behavior across voltage/temperature.
• Validate register maps, EEPROM loads, read/write protocols, and mute/test modes.
• Log and track verification bugs using GitLab and review coverage in Jama Connect.

Skills

Verilog/SystemVerilog

Cadence AMS Designer

Cadence Virtuoso

AMS/Verilog-A

Linux scripting (Python/Bash)

GitLab issue tracking

Jama Connect

Digital-Analog interface

Testbench development

Debugging top-level simulations

Education

Bachelor's or Master's in EE/CE

Tools

Cadence AMS Designer

Cadence Virtuoso

ADE Explorer/Assembler

Jama Connect

GitLab

Job description

Allegro MicroSystems, LLC is seeking a Mixed-Signal Design Verification Engineer to develop and execute top-level verification testbenches for automotive and industrial ICs. You will bridge analog blocks and digital control, running functional simulations across power sequencing and test cases to ensure first-pass silicon success.

You will collaborate with Analog, Digital Design, and Systems Engineering to review coverage metrics and support testcase closure, using Cadence AMS Designer,