Senior Memory PHY Architect — Lead High‑Speed I/O & SoCs

AMD; Santa Clara (CA); Remote; USD 150,000 - 200,000; Full time

Benefits offered by this job

Comprehensive health benefits

Flexible work arrangements

Career advancement opportunities

Job summary

A leading semiconductor company is seeking a Senior Technical Leader to shape Memory PHY technology. You will drive architectural direction and technical decisions for cutting-edge designs in mixed-signal circuits and influence critical project outcomes. Ideal candidates will have over 15 years’ experience in analog and mixed-signal design, especially in high-speed technologies. Join a collaborative team that values deep technical ownership and innovation, while shaping the future of computing architecture.

Qualifications

• 15+ years of experience in high-speed analog or mixed-signal design.
• Sustained impact on production Memory PHYs.

Responsibilities

• Serve as a senior technical authority for Memory PHY technology.
• Define architectures and specifications for advanced Memory PHYs.
• Drive innovation in high-speed I/O circuit design.

Skills

High-speed analog design

Mixed-signal design

Memory protocols

System-level analysis

Architectural influence

Education

Advanced degree in Electrical Engineering

Job description

A leading semiconductor company is seeking a Senior Technical Leader to shape Memory PHY technology. You will drive architectural direction and technical decisions for cutting-edge designs in mixed-signal circuits and influence critical project outcomes. Ideal candidates will have over 15 years’ experience in analog and mixed-signal design, especially in high-speed technologies. Join a collaborative team that values deep technical ownership and innovation, while shaping the future of computing architecture.