Senior Memory PHY Architect: High-Speed IP Design

Advanced Micro Devices, Inc.

Santa Clara (CA)

On-site

USD 180,000 - 240,000

Full time

3 days ago
Be an early applicant
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Job summary

Advanced Micro Devices, Inc. is seeking a seasoned Memory PHY Design Engineer to architect and develop high‑speed memory interface IP.

You will shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies while partnering with analog, circuit, verification, firmware, physical design, and system teams. You will influence product direction, drive power, performance, and area goals, and help establish design methodologies across programs while mentoring engineers and guiding

Qualifications

  • Bachelor’s/master’s/doctoral degree in Electrical/Computer Engineering or related field preferred.
  • Deep expertise in Memory PHY architecture for LPDDR, DDR, GDDR, or HBM.
  • Proven track record in RTL/firmware development and silicon bring-up.
  • Experience guiding multi-team technical direction and mentoring engineers.

Responsibilities

  • Define features and translate requirements into technical specs for IP.
  • Lead Memory PHY digital architecture from microarchitecture to RTL and verification.
  • Architect PHY link-layer functionality with analog and system architects.
  • Drive co-design, RTL coding, and firmware integration for high-speed interfaces.
  • Guide synthesis, timing, power optimization, and physical implementation.
  • Collaborate across teams to define and validate new product features.
  • Identify risks and drive architectural solutions meeting product goals.
  • Share knowledge and methodologies across platform teams.
  • Support post-silicon debugging of functional and performance issues.
  • Advance AI-assisted design and verification productivity.

Skills

Memory PHY architecture
Digital design
Mentor engineers
Cross-functional collaboration
Verilog/SystemVerilog
Python scripting
Power management microarchitecture
Timing closure / STA

Education

Bachelor's degree in EE/CE/CS
Master's or PhD preferred

Tools

Verilog
SystemVerilog
Python
UPF / low-power design

Job description

Advanced Micro Devices, Inc. is seeking a seasoned Memory PHY Design Engineer to architect and develop high‑speed memory interface IP.

You will shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies while partnering with analog, circuit, verification, firmware, physical design, and system teams. You will influence product direction, drive power, performance, and area goals, and help establish design methodologies across programs while mentoring engineers and guiding

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Memory PHY Architect for High-Speed Interfaces
Senior Memory PHY Architect for High-Speed Interfaces

AMD • Santa Clara (CA)

On-site
USD 180,000 - 260,000
Senior Manager, High-Speed Analog & LPDDR PHY Design
Senior Manager, High-Speed Analog & LPDDR PHY Design

AMD • California (MO)

Hybrid
USD 180,000 - 260,000
AMD benefits at a glance
Head of Analog & LPDDR PHY Design (High-Speed)
Head of Analog & LPDDR PHY Design (High-Speed)

AMD • Santa Clara (CA)

On-site
USD 180,000 - 240,000
Memory PHY Firmware Architect — Lead & Innovate
Memory PHY Firmware Architect — Lead & Innovate

Advanced Micro Devices, Inc. • Santa Clara (CA)

Hybrid
USD 170,000 - 230,000
Memory PHY Firmware Architect: Lead SoC Firmware
Memory PHY Firmware Architect: Lead SoC Firmware

AMD • Santa Clara (CA)

On-site
USD 180,000 - 240,000
Senior Memory PHY Architect — Lead High‑Speed I/O & SoCs
Senior Memory PHY Architect — Lead High‑Speed I/O & SoCs

AMD • Santa Clara (CA)

Remote
USD 150,000 - 200,000
Comprehensive health benefits
Flexible work arrangements
Career advancement opportunities
Senior Memory PHY Architect — DDR, HBM & SerDes
Senior Memory PHY Architect — DDR, HBM & SerDes

Synopsys Inc • Boxborough (MA)

On-site
USD 150,000 - 200,000
Comprehensive health benefits
Wellness programs
Financial benefits
Memory PHY Architect
Memory PHY Architect

Advanced Micro Devices, Inc. • Santa Clara (CA)

On-site
USD 180,000 - 240,000
Memory PHY Architect
Memory PHY Architect

AMD • Santa Clara (CA)

On-site
USD 180,000 - 260,000
Memory Interface Design Engineer – Hybrid Work & Growth
Memory Interface Design Engineer – Hybrid Work & Growth

ManpowerGroup Global, Inc. • Boxborough (MA)

Hybrid
USD 110,000 - 145,000
Hybrid work model
Medical plan
Dental plan
+3