Engineering Architect (Analog Mixed-Signal Architect) - 15195

Synopsys Inc; Boxborough (MA); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Comprehensive health benefits

Wellness programs

Financial benefits

Job summary

Synopsys Inc in Boxborough, MA is seeking an accomplished engineering leader to advance analog mixed-signal technology with a focus on High Bandwidth Memory (HBM) interface design. You will review multichip technologies and define design parameters to enhance performance and reliability.

The ideal candidate has over 15 years in memory design, is proficient in layout optimization, and possesses excellent communication skills. Join a dedicated team driving innovations crucial to the future of AI.

Qualifications

• 15+ years of experience in memory or die-to-die interface design.
• Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks.
• Proficiency in interposer design and implementation.

Responsibilities

• Reviewing and integrating the latest multichip and interposer technologies.
• Defining bump maps and top-level floorplans for HBM PHY products.
• Collaborating with layout teams for optimized design.

Skills

Analog mixed-signal technology

Memory interface design

Floorplan optimization

Signal integrity

Power grid design

Problem solving

Education

MS or PhD in Electrical Engineering or related field

Job description

Company Overview

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

About the Candidate

You are an accomplished engineering leader with a passion for advancing the frontiers of analog mixed‑signal technology. With a deep understanding of memory and die‑to‑die interfaces, you thrive in environments where innovation meets real‑world impact. You have a proven track record of architecting high‑performance solutions, particularly in the realm of High Bandwidth Memory (HBM) interface design. You are committed to continuous learning, keeping pace with evolving technologies and industry trends. Your communication skills enable you to articulate ideas clearly and work effectively across sites and disciplines. Above all, you are driven by the opportunity to contribute to critical components powering AI systems, knowing your work has a lasting impact on the future of technology.

Responsibilities

• Reviewing and integrating the latest multichip and interposer technologies from various foundries into Synopsys’ HBM PHY products.
• Defining bump maps and top‑level floorplans for HBM PHY products to ensure optimal performance, power, and area (PPA).
• Collaborating with layout teams to deliver top metal covercells optimized for performance and reliability in HBM PHY designs.
• Working with layout and SIPI teams to design interposer geometries that maximize performance and signal integrity.
• Mentoring junior engineers and providing technical guidance across multi‑site teams.

Impact

• Elevate the performance and reliability of Synopsys’ HBM PHY products, directly contributing to the advancement of AI and high‑performance computing systems.
• Enable successful integration of cutting‑edge multichip and interposer technologies, ensuring Synopsys remains at the forefront of semiconductor innovation.
• Improve manufacturability and scalability of memory interface IPs, supporting the needs of leading semiconductor companies worldwide.
• Drive technical excellence across cross‑functional teams, fostering collaboration and knowledge sharing.
• Enhance customer satisfaction by delivering robust, high‑quality solutions that meet demanding market requirements.
• Support Synopsys’ reputation as a trusted IP provider through leadership, innovation, and problem‑solving.

Required Qualifications

• MS or PhD in Electrical Engineering or related field.
• 15+ years of experience in memory or die‑to‑die interface design.
• Expertise in floorplan optimization for IPs integrating full‑custom analog and synthesized digital blocks.
• Strong experience with power grid design and EMIR analysis.
• Proficiency in interposer design and implementation.
• Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs).
• Deep knowledge of signal‑integrity and power‑integrity principles.
• Experience with layout impact on circuit performance and reliability.
• Ability to troubleshoot and debug memory interfaces effectively.
• Excellent communication and collaboration skills across multi‑site teams.

Desired Traits

• A collaborative leader who inspires and guides teams to technical excellence.
• Detail‑oriented, analytical, and able to balance multiple priorities.
• Innovative thinker, open to new approaches and emerging technologies.
• Effective communicator, capable of translating complex technical concepts for diverse audiences.
• Resilient and proactive in addressing challenges and driving solutions.
• Committed to continuous learning and professional growth.

Team

You’ll join our High Bandwidth Memory interface design team, a group of passionate engineers dedicated to developing best‑in‑class IP for the world’s most advanced computing systems. Our team collaborates across multiple sites and disciplines, leveraging expertise in analog mixed‑signal design, layout, and signal integrity to deliver innovative solutions that power the next generation of AI and high‑performance devices.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.