Memory Interface Design Engineer – Hybrid Work & Growth

ManpowerGroup Global, Inc.; Boxborough (MA); Hybrid; USD 110,000 - 145,000; Full time

Benefits offered by this job

Hybrid work model

Medical plan

Dental plan

Vision plan

401(k) with match

Weekly pay

Job summary

ManpowerGroup Global, Inc. is seeking a Hardware Design Engineer 2 to support the Memory PHY team. You will design RTL for high-speed memory I/O interfaces like LPDDR and DDR, and collaborate across hardware and firmware teams to deliver robust IPs.

The role emphasizes digital/analog design understanding, timing closure, and verification, with a hybrid work model requiring 2–3 days onsite.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with Verilog and SystemVerilog programming languages.
• Strong knowledge of clocking architectures, synchronization, and CDC methodology.
• Experience with synthesis, timing closure, and digital design verification tools.
• Familiarity with SERDES, DDR, Memory Controller, or MAC design is preferred.

Responsibilities

• Design RTL for high-speed memory I/O PHY interfaces, including LPDDR and DDR IPs.
• Develop digital architecture from concept to physical implementation, ensuring optimal performance.
• Collaborate with architects, hardware, and firmware engineers to integrate new features.
• Perform timing synthesis, physical implementation, and verification of memory interface designs.
• Debug design failures, identify root causes, and work with teams to resolve issues efficiently.

Skills

Verilog

SystemVerilog

C

C++

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Timing closure tools

Digital design verification tools

SERDES

DDR

Job description

ManpowerGroup Global, Inc. is seeking a Hardware Design Engineer 2 to support the Memory PHY team. You will design RTL for high-speed memory I/O interfaces like LPDDR and DDR, and collaborate across hardware and firmware teams to deliver robust IPs.

The role emphasizes digital/analog design understanding, timing closure, and verification, with a hybrid work model requiring 2–3 days onsite.