Sr. Fellow -- Memory PHY Architect

AMD; Santa Clara (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Comprehensive health benefits

Flexible work arrangements

Career advancement opportunities

Job summary

A leading semiconductor company is seeking a Senior Technical Leader to shape Memory PHY technology. You will drive architectural direction and technical decisions for cutting-edge designs in mixed-signal circuits and influence critical project outcomes. Ideal candidates will have over 15 years’ experience in analog and mixed-signal design, especially in high-speed technologies. Join a collaborative team that values deep technical ownership and innovation, while shaping the future of computing architecture.

Qualifications

• 15+ years of experience in high-speed analog or mixed-signal design.
• Sustained impact on production Memory PHYs.

Responsibilities

• Serve as a senior technical authority for Memory PHY technology.
• Define architectures and specifications for advanced Memory PHYs.
• Drive innovation in high-speed I/O circuit design.

Skills

High-speed analog design

Mixed-signal design

Memory protocols

System-level analysis

Architectural influence

Education

Advanced degree in Electrical Engineering

Job description

Job Summary

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers to PCs, gaming and embedded systems.

Grounded in a culture of innovation and collaboration, we strive for execution excellence while being direct, humble, collaborative and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Role

This role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture and delivery of next‑generation Memory PHY solutions in advanced CMOS technologies.

The focus is long‑term impact: setting technical direction, guiding critical design decisions and enabling teams to deliver differentiated mixed‑signal IP across future SoCs.

This position is well suited for technologists who value deep technical ownership, architectural influence and the ability to leave a lasting technical legacy without requiring people‑management as a primary responsibility.

The Person

You are a highly respected engineer or architect known for solving difficult problems and raising the technical bar around you. You bring perspective earned from experience, approach challenges with curiosity and pragmatism, and engage others through thoughtful collaboration rather than authority. You are comfortable operating with ambiguity, influencing across organizations, and contributing at both strategic and hands‑on technical levels.

Key Responsibilities

• Serve as a senior technical authority and architect for Memory PHY technology, shaping long‑range roadmaps and architectural direction.
• Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR and HBM.
• Drive innovation in high‑speed I/O circuit design, system‑level analysis, power integrity and signal integrity.
• Partner with cross‑functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification and Post‑Silicon organizations worldwide.
• Influence design quality and execution through design reviews, technical mentorship and principled trade‑off decisions.
• Support post‑silicon bring‑up, validation, characterization, optimization and product readiness.
• Communicate complex technical concepts clearly to senior technical peers, leadership and stakeholders.
• Mentor and advise engineers and architects, contributing to a strong and inclusive technical community.

Preferred Experience

• Sustained technical impact on production Memory PHYs or high‑speed I/O IP at advanced technology nodes.
• Experience owning or shaping architecture across multiple successful tape‑outs.
• Deep expertise in high‑speed analog and mixed‑signal design, memory protocols and system‑level considerations.
• Strong understanding of advanced CMOS technologies and modern design methodologies.
• Track record of making sound technical decisions in complex, high‑risk design spaces.
• Ability to influence without formal authority and collaborate effectively across organizational boundaries.

Academic Credentials

• Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience.
• Typically, 15+ years of experience in high‑speed analog, mixed‑signal or memory PHY design.

Location

Flexible – Bay Area, CA; Boston, MA; Austin, TX; or Toronto, Canada.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.