Senior Memory Packaging Engineer - High-Density Co-Design

Apple, Inc.; San Diego (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Apple benefits

Employee stock purchase plan

Relocation assistance

Job summary

Apple seeks a Memory Packaging Engineer in San Diego, CA to architect memory solutions powering the performance of our hardware. You will guide the package roadmaps and own the lifecycle from concept through qualification, collaborating with internal teams and memory partners to enable bandwidth and density scaling.

You will drive materials development, thermal and mechanical integration, and vendor engagement for state-of-the-art memory packages, with deep experience in high-bandwidth,

Qualifications

• BS degree and 10+ years of relevant industry experience.
• Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding.
• Experience in packaging design, assembly process development, and reliability testing.

Responsibilities

• Determine the direction of next-generation package architecture by evaluating available and emerging packaging technologies.
• Collaborate with cross-functional teams to solve integration challenges, including electrical, mechanical, and thermal.
• Drive vendor DOEs and failure analysis to improve downstream yield and maintain world-class quality and reliability.
• Define the memory package POR: Package form factor, process, layout, stackup, and BOM.
• Drive memory vendors to develop package materials and technology for leading-edge package design rules.

Skills

Thin-die stacking

Wirebonding

Flip-chip

Wafer bonding

Packaging materials

Thermal mitigation

Test & reliability

SI/PI co-design

Die floorplanning

Vendor collaboration

Education

Bachelor's degree

MS or PhD preferred

Job description

Apple seeks a Memory Packaging Engineer in San Diego, CA to architect memory solutions powering the performance of our hardware. You will guide the package roadmaps and own the lifecycle from concept through qualification, collaborating with internal teams and memory partners to enable bandwidth and density scaling.

You will drive materials development, thermal and mechanical integration, and vendor engagement for state-of-the-art memory packages, with deep experience in high-bandwidth,