Senior IC Layout Engineer - SerDes & Analog Lead

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices, Inc. (AMD) seeks an experienced analog/mixed-signal layout design engineer with supervisory responsibilities in San Jose, CA. The role focuses on high-speed SerDes layout, floorplanning, power distribution, and timing-aware transistor-level layout.

You will collaborate with engineers across time zones, drive layout methodology, and help optimize productivity while ensuring layout quality and integration readiness.

Qualifications

• Bachelor's degree in EE/CE or IC layout with hands-on layout experience.
• High-speed analog/mixed-signal layout expertise required.
• Experience with multi-site teams and tight schedules.
• Familiarity with IC fabrication processes and LVS/DRC checks.

Responsibilities

• Layout design for high-speed SerDes analog/mixed-signal circuits.
• Block-level physical implementation: floorplanning, power/clock routing, layout.
• Post-layout performance analysis participation.
• Support block/IP/chip integration activities with teams across sites.
• Estimate schedules and report progress; drive layout productivity improvements.
• Mentor layout resources onsite and offsite; address quality issues.

Skills

High-speed layout

Analog/mixed-signal layout

Supervisory/leadership

Team collaboration

Problem solving

Education

BSc in EE/CE or IC layout training

Tools

Cadence SKILL

Programming (Perl, Python, Tcl)

Job description

Advanced Micro Devices, Inc. (AMD) seeks an experienced analog/mixed-signal layout design engineer with supervisory responsibilities in San Jose, CA. The role focuses on high-speed SerDes layout, floorplanning, power distribution, and timing-aware transistor-level layout.

You will collaborate with engineers across time zones, drive layout methodology, and help optimize productivity while ensuring layout quality and integration readiness.