Senior Analog Design Lead for High-Speed IPs (HBM)

Micron Technology, Inc.; Richardson (TX); On-site; USD 180,000 - 280,000; Full time

Job summary

Micron Technology, Inc. is seeking a Principal Analog Design Engineer to lead the design, integration and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products.

You will drive end-to-end silicon execution, layout-aware optimizations and IP interfaces across subsystems. You will provide deep technical leadership in high-speed analog design, biasing and power management, SPICE modeling, and silicon bring-up, partnering with layout, digital, and test teams to

Qualifications

• MS or PhD in Electrical Engineering or related field required.
• ~10-15+ years of analog/mixed-signal IC experience preferred.
• Experience with high-speed analog/mixed-signal IP development is essential.

Responsibilities

• Lead the design and own critical HBM analog circuits, including high-speed transmitters and receivers.
• Define and lead IP interfaces, power domains, clocking schemes, and reset strategies across subsystems.
• Perform detailed pre-layout and post-layout simulations; conduct PVT, Monte Carlo, mismatch, and aging analyses.
• Collaborate with layout engineers to ensure matching, shielding, EM/IR compliance, and floorplanning.
• Review and sign off on analog layouts; drive layout-aware build optimizations for advanced nodes.
• Define guidelines for analog build, documentation, and reuse; collaborate with analog, digital, system, packaging, and test teams.

Skills

High-speed interface design

Clocking circuits (PLL/DLL/CDR)

Power management circuits

Analog IP integration at subsystem or

SPICE simulation, extraction, and \u00

Education

MS or PhD in Electrical Engineering

Job description

Micron Technology, Inc. is seeking a Principal Analog Design Engineer to lead the design, integration and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products.

You will drive end-to-end silicon execution, layout-aware optimizations and IP interfaces across subsystems. You will provide deep technical leadership in high-speed analog design, biasing and power management, SPICE modeling, and silicon bring-up, partnering with layout, digital, and test teams to