Principal ASIC Engineer [Reliability & Hardware Validation] Hybrid

Anysilicon; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Cisco in San Jose, CA seeks a Principal ASIC Engineer to lead reliability and hardware design validation for next‑gen networking products in a hybrid role. You will define qualification plans, manage HTOL and Burn‑In testing, and collaborate across eCAD, FPGA, Power, Mechanical and SI teams to ensure reliability and compliance.

You'll apply JEDEC/AEC/Telcordia standards, perform failure analyses, and deliver detailed qualification reports.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of professional experience in semiconductor reliability or high-speed hardware design.
• Experience developing HTOL/Burn-In testing for advanced node products.
• Hands-on experience with high-speed network interfaces and board design.

Responsibilities

• Define and execute comprehensive product/process qualification plans for high-power solutions.
• Drive robust HTOL, Burn-In, and stress testing, managing reliability suppliers to meet qualification schedules.
• Lead hardware design, schematic generation, and validation for service provider routing products.
• Conduct failure analysis and generate detailed qualification reports to ensure product integrity.
• Collaborate with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams for design-for-reliability and compliance.
• Provide technical documentation and support for customer quality and reliability requirements.

Skills

Semiconductor standards

High-speed testing

Data analysis

HTOL setup

Education

Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Cadence Allegro

Job description

Principal ASIC Engineer [Reliability & Hardware Validation] Hybrid

Cisco is seeking a highly skilled Engineer to lead reliability and hardware design validation for next-generation semiconductor and networking products in a hybrid role based in San Jose, California. This position is part of the Cisco Hardware Engineering Team, which focuses on developing innovative hardware solutions that adhere to industry standards and enhance user experience.

Responsibilities:

• Define and execute comprehensive product/process qualification plans for high-power solutions.
• Drive robust HTOL, Burn-In, and stress testing, managing reliability suppliers to meet qualification schedules.
• Lead hardware design, schematic generation, and validation for service provider routing products.
• Conduct failure analysis and generate detailed qualification reports to ensure product integrity.
• Collaborate with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams for design-for-reliability and compliance.
• Provide technical documentation and support for customer quality and reliability requirements.

Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
• Proven experience in developing high-power HTOL/Burn-In testing for advanced node products.
• Hands-on experience with high-speed network interfaces and board design.

Skills:

• Deep knowledge of JEDEC, AEC, and Telcordia standards.
• Experience with high-speed measurement equipment and automated test development.
• Proficiency in data analysis/debug and HTOL set-up.
• Familiarity with tools such as Cadence Allegro.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Work Email

Free No obligation Response within 24 hours