ASIC Design Engineer 2

Anysilicon; Sunnyvale (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) seeks an ASIC Design Engineer 2 to join the Juniper Silicon group in Sunnyvale, CA. Onsite role focusing on advanced networking chips and collaboration with cross-functional teams.

Responsibilities include developing micro-architecture specs, RTL coding, and ensuring timing and verification using modern EDA tools. Strong foundation in digital design and system Verilog is required.

Qualifications

• BS in Electrical Engineering required.
• Master's degree strongly desired.
• Coursework in digital logic essential.
• Strong analytical and problem-solving skills.

Responsibilities

• Develop micro-architecture specs from functional specs under guidance.
• Perform RTL coding in SystemVerilog for projects.
• Create functional coverage and SVA; training provided if needed.
• Collaborate with PD to fix RTL timing to meet targets.
• Debug verification issues using advanced EDA tools.

Skills

Verilog/SystemVerilog

RTL coding

SVA

Python/Perl

Analytical skills

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

SystemVerilog simulators

EDA tools

Git

Job description

Job Description:

Hewlett Packard Enterprise (HPE) is seeking an ASIC Design Engineer 2 to join their Juniper Silicon group, focusing on the design of advanced networking chips. This role is primarily onsite and offers a dynamic environment where innovation and teamwork are emphasized. HPE values diverse backgrounds and provides opportunities for personal and professional growth.

Responsibilities:

• Develop detailed micro-architecture specifications from functional specifications with guidance from senior engineers.
• Perform RTL coding, preferably in System Verilog, and engage in coding projects.
• Write functional coverage and System Verilog Assertions (SVA) with training provided if necessary.
• Collaborate with Physical Design (PD) teams to identify and resolve timing issues in RTL to meet frequency targets.
• Debug issues identified by the verification team using state-of-the-art EDA tools.

Qualifications:

• Bachelor’s degree in Electrical Engineering required; Master’s degree strongly desired.
• Completion of courses in digital logic design is essential.
• Strong analytical and problem-solving skills.

Skills:

• Proficient coding skills in Verilog/System Verilog through academic and internship projects.
• Knowledge of computer architecture, networking protocols, and machine learning is a plus.
• Familiarity with Perl/Python is advantageous.
• Excellent written and verbal communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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