Senior FPGA Debug & Verification Architect

191 Altera Corporation; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

191 Altera Corporation is seeking a Sr. Debug Design Verification Engineer responsible for Design for Debug architecture verification tasks, including creating test cases and test benches using UVM methodology. Candidates must have a minimum of 8 years of experience in complex ASIC designs and proficiency in SystemVerilog.

The role includes pre-silicon system verification and requires strong communication skills to coordinate with cross-functional teams. The salary range for this position is between $149,100 and $215,000 USD.

Qualifications

• 8+ years of experience with complex ASIC designs and/or verification.
• Strong proficiency in SystemVerilog and UVM verification.
• Minimum of 8 years scripting in Linux/Unix environments.

Responsibilities

• Pre-silicon system verification for SoC, FPGA & Full Chip.
• Create test cases and test benches using UVM methodology.
• Coordinate with Design, SW, Architecture teams for verification.

Skills

SystemVerilog

UVM verification methodology

Scripting in Linux/Unix

Communication skills

Tools

Perl

Python

Job description

191 Altera Corporation is seeking a Sr. Debug Design Verification Engineer responsible for Design for Debug architecture verification tasks, including creating test cases and test benches using UVM methodology. Candidates must have a minimum of 8 years of experience in complex ASIC designs and proficiency in SystemVerilog.

The role includes pre-silicon system verification and requires strong communication skills to coordinate with cross-functional teams. The salary range for this position is between $149,100 and $215,000 USD.