Senior Lead Full-Chip SoC Layout & Integration Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 122,000 - 232,000; Full time

Benefits offered by this job

Hybrid work model

Stock bonuses

Health benefits

Job summary

Intel Corporation in Hillsboro, OR is seeking an experienced engineer for the X-Chip Full-Chip Integration team to lead full-chip floorplanning, layout integration, and tapeout for advanced-node silicon development vehicles.

You will develop custom layout methodologies, drive physical verification, collaborate with PDK and EDA teams, and advance designs through tape-in and silicon validation. Strong scripting and cross-functional collaboration are essential.

Qualifications

• Master's degree in Electrical/Computer Engineering with 4+ years industry experience.
• OR PhD with 1+ year industry experience.
• Custom/analog/mixed-signal layout on advanced technology nodes.
• Front-end layout rules, transistor matching, parasitic concepts.
• Debugging physical verification with LVS/DRC/DFM using Calibre or ICV.
• Automation using Tcl/Python/SKILL for layout tasks.

Responsibilities

• Lead full-chip floorplanning, integration, and tapeout for advanced-node vehicles.
• Develop and refine custom layout methodologies and flows.
• Drive physical verification closure (DRC/LVS/DFM).
• Collaborate with PDK, Technology Development, and EDA teams.
• Analyze rules for design enablement in FinFET/GAA.
• Develop automation to improve productivity and quality.
• Coordinate tape-in readiness and project execution.
• Communicate tradeoffs and make sound technical decisions.

Skills

Custom/analog/mixed-signal layout

FEOL layout rules

Layout debugging (LVS/DRC)

Automation scripting (Tcl/Python/SKILL

Full-chip integration

Cross-team collaboration

Education

Master's degree in Electrical/Computer Engineering

PhD in EE or related field

Tools

Cadence Virtuoso

Calibre

Job description

Intel Corporation in Hillsboro, OR is seeking an experienced engineer for the X-Chip Full-Chip Integration team to lead full-chip floorplanning, layout integration, and tapeout for advanced-node silicon development vehicles.

You will develop custom layout methodologies, drive physical verification, collaborate with PDK and EDA teams, and advance designs through tape-in and silicon validation. Strong scripting and cross-functional collaboration are essential.