Layout Engineer

Rise Technical Recruitment Limited; Plano (TX); On-site; USD 110,000 - 130,000; Full time

Benefits offered by this job

Stock Options

Health Benefits

401(k)

Training & Development

Space/Defense tech exposure

Job summary

Rise Technical Recruitment Limited is seeking an IC Layout Engineer for a Plano-based role in the Dallas–Fort Worth area. You will own full-chip layouts from floorplan to tapeout and work on power/ground grids, ESD structures, and verification flows.

The position targets candidates with strong analog/digital layout fundamentals and experience with LVS/DRC tools. On-site role with a fabless semiconductor focus and opportunities in aerospace/space tech.

Qualifications

• Experience with full-chip IC layout from floorplan to tapeout
• Strong LVS/DRC verification knowledge
• Solid analog and digital layout fundamentals

Responsibilities

• Own full-chip IC layout from floorplan through tapeout (.gds/.oasis)
• Develop power/ground grids, routing/channel planning and EMI considerations
• Implement ESD structures and document verification flows
• Collaborate with design engineers, project owners, foundry and contractors

Skills

Full-chip layout ownership

Analog/digital layout fundamentals

Tools

Cadence

PVS/Assura/Calibre

KiCad

Job description

Salary: USD110000 - USD130000 per annum + Stock Options + Benefits

IC Layout Engineer / Semiconductor Layout Engineer

$110,000 - $130,000 + Stock Options + Health Benefits + 401(k) + Technical Training & Development + Cutting-Edge Space/Defense Tech

On-site role in Plano, Texas (Dallas-Fort Worth area)

Are you an IC Layout Engineer or Semiconductor Layout Engineer looking for a role where you can own full-chip layouts through tapeout, keep learning in a fast-moving environment, and work on cutting-edge technology built for spacecrafts and satellites?

On offer is a secure, permanent position with a growing specialist semiconductor business that invests in technical development and gives you real ownership across the layout lifecycle.

This is a fabless team known for innovative radiation-hardened ICs used on spacecrafts. As a result of continued growth and ongoing contracts, they are now adding to their layout function.

In this role you will lead floorplanning from chip boundary down to leaf-cell level, build and maintain power/ground grids, implement ESD structures, support standard-cell library work, and run LVS/DRC using industry tools, while partnering with design, project owners, and foundry stakeholders.

This role would suit a Layout Engineer with strong analog/digital layout fundamentals looking for high-impact ownership, continuous technical development, and the chance to work on advanced ICs for demanding environments.

The Role:

• Own full-chip IC layout from floorplan through tapeout (.gds/.oasis)
• Power/ground grid development, routing/channel planning, EMIR/voltage-drop considerations, and ECO-friendly "future-proofing"
• ESD cell implementation, documentation of verification flows, and weekly layout status updates
• Cross-functional collaboration with design engineering, project owners, foundry, and (as needed) external contractors

The Person:

• IC/semiconductor layout experience across modern process nodes
• Experience with LVS/DRC verification and layout tools (Cadence and/or similar; PVS/Assura/Calibre; KiCad)
• Strong understanding of layout integrity topics (ESD, latch-up, antenna, cross-talk/coupling, EMIR mitigation)

Reference Number: BBBH280653