IC Layout Engineer

Rise Technical Recruitment Limited; Plano (TX); Presencial; USD 110 000 - 130 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Stock options

Health benefits

401(k)

Technical training

Resumo da oferta

Rise Technical Recruitment Limited is seeking an IC Layout Engineer for a fabless semiconductor specialist in Plano, Texas. You will own full-chip layouts from floorplan through tapeout and contribute to radiation‑hardened ICs for spacecrafts, offering strong ownership and ongoing technical development.

You will lead floorplanning, power/ground grid work, ESD structures, and standard-cell library support, using LVS/DRC tooling and collaborating with design engineers, project owners, and

Qualificações

• Experience in IC/semiconductor layout across modern nodes.
• Strong LVS/DRC verification knowledge with layout tools.
• Solid understanding of layout integrity topics (ESD, latch-up, cross-talk).

Responsabilidades

• Own full-chip IC layout from floorplan through tapeout (.gds/.oasis).
• Develop power/ground grids and routing plans.
• Implement ESD structures and document verification flows.
• Collaborate with design engineering, project owners, foundry, and contractors.
• Work on-site in Plano, Texas as a full-time role.

Conhecimentos

LVS/DRC verification

Layout fundamentals

Analog/digital layout

Cross-functional collaboration

Ferramentas

Cadence

PVS/Assura/Calibre

KiCad

Descrição da oferta de emprego

Salary: USD110000 - USD130000 per annum + Stock Options + Benefits

IC Layout Engineer / Semiconductor Layout Engineer

$110,000 - $130,000 + Stock Options + Health Benefits + 401(k) + Technical Training & Development + Cutting-Edge Space Semiconductor Tech

On-site role in Plano, Texas (Dallas-Fort Worth area)

Are you an IC Layout Engineer or Semiconductor Layout Engineer looking for a role where you can own full-chip layouts through tapeout, keep learning in a fast-moving environment, and work on cutting-edge technology built for spacecrafts and satellites?

On offer is a secure, permanent position with a growing specialist semiconductor business that invests in technical development and gives you real ownership across the layout lifecycle.

This is a fabless team known for innovative radiation-hardened ICs used on spacecrafts. As a result of continued growth and ongoing contracts, they are now adding to their layout function.

In this role you will lead floorplanning from chip boundary down to leaf-cell level, build and maintain power/ground grids, implement ESD structures, support standard-cell library work, and run LVS/DRC using industry tools, while partnering with design, project owners, and foundry stakeholders.

This role would suit a Layout Engineer with strong analog/digital layout fundamentals looking for high-impact ownership, continuous technical development, and the chance to work on advanced ICs for demanding environments.

The Role:

• Own full-chip IC layout from floorplan through tapeout (.gds/.oasis)
• Power/ground grid development, routing/channel planning, EMIR/voltage-drop considerations, and ECO-friendly "future-proofing"
• ESD cell implementation, documentation of verification flows, and weekly layout status updates
• Cross-functional collaboration with design engineering, project owners, foundry, and (as needed) external contractors
• Full-time, on-site position based in Plano, Texas

The Person:

• IC/semiconductor layout experience across modern process nodes
• Experience with LVS/DRC verification and layout tools (Cadence and/or similar; PVS/Assura/Calibre; KiCad)
• Strong understanding of layout integrity topics (ESD, latch-up, antenna, cross-talk/coupling, EMIR mitigation)

Reference Number: BBBH280653