Senior Lead Analog CMOS Layout Engineer

Sitime-Corporation; Santa Clara (CA); On-site; USD 125,000 - 172,000; Full time

Benefits offered by this job

401k plan

Health and wellness

Job summary

SiTime is seeking a Senior Layout Design Engineer in Santa Clara, CA to lead top-chip and block- level Analog Layout design for CMOS/BiCMOS circuits. You will coordinate offshore layouts, mentor juniors, and drive standard methodologies to ensure high-quality layouts.

Responsibilities include floorplanning, routing, verification (DRC/LVS/ERC), and tape-out support across global teams. Strong Cadence Virtuoso and Calibre skills are required.

Qualifications

• BA/BS in Layout Design or related field, or equivalent experience.
• 15+ years of experience in layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm process technologies.
• Proficiency with Cadence Virtuoso; DRC/LVS/ERC debugging using PVS or Mentor Calibre.
• Understanding of parasitics, matching, crosstalk, LDE, latch-up, IR drop, EM, NTN isolation.
• Experience with chip-level floorplanning and analog block integration; tape-out.
• Ability to use productivity-enhancing scripts to automate workflows.
• Must be able to lift up to 5 lbs.

Responsibilities

• Collaborate remotely with local and global design and layout teams across centers and time zones.
• Lead and perform custom analog layout design at chip and block levels for CMOS/BiCMOS.
• Execute schematic-driven layout while adhering to constraints.
• Create area-efficient functional block layouts meeting circuit requirements.
• Develop top-chip floor plans, power networks, shielding, and device-matching layouts.
• Verify layouts and ensure DRC, LVS, and ERC signoff.
• Perform chip-level routing and other layout activities.
• Own chip-chip integration, verification, and tape-out activities.
• Train and mentor junior layout engineers and offshore contractors.
• Contribute to common best practices and workflows across sites.
• Help establish and improve processes to achieve high layout quality.

Skills

layout design

analog layout

full-custom digital blocks

Cadence Virtuoso

DRC/LVS/ERC

parasitics/matching

team leadership

scripting/automation

Education

BA/BS in Layout Design or related field

Tools

Cadence Virtuoso

Mentor Calibre

PVS debugging

Job description

SiTime is seeking a Senior Layout Design Engineer in Santa Clara, CA to lead top-chip and block- level Analog Layout design for CMOS/BiCMOS circuits. You will coordinate offshore layouts, mentor juniors, and drive standard methodologies to ensure high-quality layouts.

Responsibilities include floorplanning, routing, verification (DRC/LVS/ERC), and tape-out support across global teams. Strong Cadence Virtuoso and Calibre skills are required.