Senior/Principal High-Speed Analog Layout Architect (Remote)

Celero Communications, Inc.; Irvine (CA); Remote; USD 150,000 - 210,000; Full time

Benefits offered by this job

Foundational role at fast-growing sem1

International team culture

Exposure to cross functional teams

Job summary

Celero Communication Inc. is seeking a Principal/Senior High-Speed Analog Layout Engineer to drive layout for ADCs, DACs, PLLs and other high-performance blocks.

You will lead cross-functional layout efforts, mentor engineers across time zones, and ensure first-pass silicon success through rigorous checks. This hands-on role requires strong Cadence/Calibre experience, deep device physics understanding, and proven leadership in complex IP layout at FinFET nodes.

Qualifications

• Minimum 10+ years of hands-on analog/mixed-signal layout design experience.
• Experience leading IP layout macros or full-chip-level layout at FinFET nodes.
• Knowledge of TSMC FinFET process nodes (N3/N5/N7/N16).
• Expertise in layout best practices for matching, noise isolation, ESD, symmetry, and parasitics.
• Familiarity with LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to optimize performance, matching, symmetry, and reliability.
• Mentor junior layout engineers/contractors across time zones and enforce best practices.
• Perform and debug LVS, DRC, PERC, ERC and other signoff checks using industry tools.
• Contribute to chip-level planning including floor planning, block integration, and power grid design.
• Lead layout design reviews and drive quality, verification, and schedule adherence.
• Support automation through scripting (SKILL, TCL, Python).

Skills

Leadership

Mentoring

Documentation

Cross-functional collaboration

Signal integrity

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC/PERC/ERC

Python/Skill scripting

Job description

Celero Communication Inc. is seeking a Principal/Senior High-Speed Analog Layout Engineer to drive layout for ADCs, DACs, PLLs and other high-performance blocks.

You will lead cross-functional layout efforts, mentor engineers across time zones, and ensure first-pass silicon success through rigorous checks. This hands-on role requires strong Cadence/Calibre experience, deep device physics understanding, and proven leadership in complex IP layout at FinFET nodes.