Analog Layout Engineer - Senior Consultant

Redolent Infotech Pvt. Ltd.; San Jose (CA); On-site; USD 180,000 - 240,000; Part time

Job summary

Redolent Infotech Pvt. Ltd. in San Jose, CA is seeking an experienced Analog Layout Engineer for an onsite, six-month contracting position.

You will lead the layout of high-performance analog cores, including ADCs, DACs and PLLs, across multiple CMOS nodes. The role requires 10+ years of analog layout experience in advanced CMOS processes, strong knowledge of Cadence, Mentor, and Synopsys tools, and proven collaboration with distributed teams.

Qualifications

• Thorough knowledge of Cadence, Mentor, and Synopsys EDA tools.
• Set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Experience with layout of high-performance analog blocks such as ADCs, DACs, PLLs.
• Experience with floor planning, block-level routing, and top-level chip assembly.
• Knowledge of high-performance analog layout techniques (centroid, shielding, dummy devices, thermal aware layout).
• Experience with analog layout in silicon mass production.
• FinFET process node experience preferred.
• Onsite role with strong written and verbal communication skills.
• 10+ years experience in high-performance analog layout in advanced CMOS processes.

Responsibilities

• The senior layout designer will be responsible for the layout of high-performance analog cores such as ADCs, DACs, PLLs, and transceivers.
• Lead IC layout across multiple nodes and ensure best-practice CMOS layout.
• Collaborate with distributed design teams and adhere to schedules.

Skills

Analog Layout

CMOS processes

Floorplanning

Team collaboration

Communication

FinFET

Mass production

Education

No specific degree stated

Tools

Cadence

Mentor

Synopsys

Job description

• San Jose, CA

Hello,

One of our direct client is urgently looking for Analog Engineer @ San Jose, CA

Role - Analog Layout Engineer

Location - San Jose, CA

Contracting Position (six months with possible extension)

Experience in - 16nm TSMC OR 14nm OR 22nm Intel

Responsibilities

• The senior layout designer will be responsible for the layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
• Responsibilities include leading IC layout of cutting-edge high performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
• This is an onsite role.

Qualifications

• Thorough knowledge of industry-standard EDA tools from Cadence, Mentor, and Synopsys.
• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
• Experience with floor planning, block-level routing, and top-level chip assembly.
• Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
• Demonstrated experience with the analog layout for silicon chips in mass production.
• Experience with FinFET process nodes preferred
• Experience working with distributed design teams is a plus.
• Knowledge of skill code layout automation is a plus.
• Self-starter with the ability to define and adhere to a schedule.
• Must possess strong written and verbal communication skills.
• 10+ years experience in high-performance analog layout in advanced CMOS processes.