Lead Analog Layout Architect for High-Speed IPs

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA seeks a Senior/Principal Analog Layout Engineer to lead complex analog/mixed-signal layout development for high-performance IP blocks. You will mentor, coordinate with CAD/PDK teams, and drive first-pass silicon success in a fast-paced environment.

You will own floor planning, block integration, and rigorous signoff checks using Cadence Virtuoso, Calibre, and Pegasus, contributing to scalable layouts and automation efforts across global teams.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout in CMOS/FinFET.
• Track record of top-level IP layout macros and handoff readiness.
• Leadership in owning IP layout macros or full-chip layout at FinFET nodes (TSMC).
• At least 1 year of experience with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of LOD, WPE, OSE, LDE and impact on performance.
• Expertise in matching, noise isolation, ESD, symmetry, and minimization of parasitics.
• Floor planning, hierarchical integration, routing strategy, and power/ground design.
• Proficiency with LVS/DRC/PERC/DFM/ERC and antenna rules.
• Experience working with international/remote teams and strong documentation.
• Familiarity with revision control for layout design management.

Responsibilities

• Lead the physical layout design of analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize performance, matching and reliability.
• Mentor junior layout engineers and contractors across time zones.
• Perform and debug LVS, DRC, PERC, ERC and other signoff checks with standard tools.
• Contribute to chip-level planning, power grid, and signal routing.
• Lead layout design reviews and ensure quality, verification completeness and schedule adherence.
• Support automation through scripting and tool customization (SKILL, TCL, Python).

Skills

Analog layout

Mixed-signal layout

Mentoring

Schematic-layout collaboration

Hierarchy LVS/DRC

Floor planning

Routing & power grid

Layout verification tools

International collaboration

Tools

Cadence Virtuoso

Calibre

Pegasus

Revision control (Git)

Job description

Celero Communications, Inc. in Irvine, CA seeks a Senior/Principal Analog Layout Engineer to lead complex analog/mixed-signal layout development for high-performance IP blocks. You will mentor, coordinate with CAD/PDK teams, and drive first-pass silicon success in a fast-paced environment.

You will own floor planning, block integration, and rigorous signoff checks using Cadence Virtuoso, Calibre, and Pegasus, contributing to scalable layouts and automation efforts across global teams.