Senior IP Verification Architect for High-Speed Protocols

191 Altera Corporation; San Jose (CA); On-site; USD 142,600 - 206,500; Full time

Job summary

191 Altera Corporation seeks a Lead DV Engineer based in San Jose, California, focusing on IP verification and validation. The role involves verifying IP functionality, developing testbenches, and collaborating with cross-functional teams to enhance IP quality.

The ideal candidate has extensive experience in verification methods, particularly with Verilog, System Verilog, and UVM, and will work on achieving high-quality standards within aggressive deadlines.

The salary range for this position is $142.6k - $206.5k USD based on various factors.

Qualifications

• 9+ years of industry experience in verification.
• 7+ years with Ethernet/PCIe/CXL protocol verification.
• 7+ years in developing coverage-driven random constraint UVM environments.

Responsibilities

• Verify and validate IP for robust functionality.
• Create comprehensive verification and validation plans.
• Develop system level testbenches and create necessary tests.

Skills

Verilog

System Verilog

UVM

Debugging skills

Communication skills

Education

BS/MS in Electrical Engineering or Computer Engineering

Job description

191 Altera Corporation seeks a Lead DV Engineer based in San Jose, California, focusing on IP verification and validation. The role involves verifying IP functionality, developing testbenches, and collaborating with cross-functional teams to enhance IP quality.

The ideal candidate has extensive experience in verification methods, particularly with Verilog, System Verilog, and UVM, and will work on achieving high-quality standards within aggressive deadlines.

The salary range for this position is $142.6k - $206.5k USD based on various factors.