ALTEN is seeking a verification engineer in San Jose, California, to own the verification for various blocks in a SoC and develop comprehensive strategies. The role requires experience in digital verification, communication, and problem solving. Preferred qualifications include knowledge in System Verilog, UVM, and AMBA bus protocols. Candidates should demonstrate strong teamwork and effective communication skills to work closely with design teams.
Qualifications
Experience with digital verification aspects like test automation, code and functional coverage.
Prior experience with System Verilog Assertions and Code/Functional Coverage.
Strong communication and problem-solving skills.
Responsibilities
Own verification for various blocks in a SoC, sub-system or IP.
Develop a comprehensive verification strategy.
Work with cross-functional IP teams for integration verification.
Skills
Digital verification
Problem solving
Communication
Test automation
System Verilog
UVM
Scripting (Perl/Python)
Tools
Verilog/System Verilog
AMBA bus protocols
Job description
ALTEN is seeking a verification engineer in San Jose, California, to own the verification for various blocks in a SoC and develop comprehensive strategies. The role requires experience in digital verification, communication, and problem solving. Preferred qualifications include knowledge in System Verilog, UVM, and AMBA bus protocols. Candidates should demonstrate strong teamwork and effective communication skills to work closely with design teams.