Lead IP Verification Engineer – High‑Speed Protocols

Altera

San Jose (CA)

On-site

USD 142,600 - 206,500

Full time

14 days+

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Job summary

Altera is seeking a Lead DV Engineer to focus on IP Verification & Validation in San Jose, California. The role involves developing comprehensive validation plans and collaborating with cross-functional teams to ensure robust IP functionality.

The ideal candidate has over 9 years of experience in verification processes, specifically with high-speed protocols like Ethernet/PCIe/CXL. A competitive salary range of $142.6k - $206.5k USD is offered, based on location and experience.

This role contributes significantly to enhancing the quality and usability of Altera's FPGA IP product portfolios.

Qualifications

  • 9+ years of industry experience in verification and validation.
  • Strong experience in developing verification collateral in Verilog and System Verilog.
  • Expertise in UVM with a focus on constraint random test environments.

Responsibilities

  • Create verification and validation plans for IP across Altera FPGA portfolios.
  • Develop testbenches, write test cases, and debug failures.
  • Establish validation coverage strategies and maximize IP quality.

Skills

Verilog
System Verilog
UVM
Ethernet protocol verification
PCIe protocol verification
CXL protocol verification
Debugging skills

Education

BS/MS in Electrical Engineering, Computer Engineering or related field

Tools

IP/FPGA validation tools

Job description

Altera is seeking a Lead DV Engineer to focus on IP Verification & Validation in San Jose, California. The role involves developing comprehensive validation plans and collaborating with cross-functional teams to ensure robust IP functionality.

The ideal candidate has over 9 years of experience in verification processes, specifically with high-speed protocols like Ethernet/PCIe/CXL. A competitive salary range of $142.6k - $206.5k USD is offered, based on location and experience.

This role contributes significantly to enhancing the quality and usability of Altera's FPGA IP product portfolios.

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