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Altera is seeking a Lead DV Engineer to focus on IP Verification & Validation in San Jose, California. The role involves developing comprehensive validation plans and collaborating with cross-functional teams to ensure robust IP functionality.
The ideal candidate has over 9 years of experience in verification processes, specifically with high-speed protocols like Ethernet/PCIe/CXL. A competitive salary range of $142.6k - $206.5k USD is offered, based on location and experience.
This role contributes significantly to enhancing the quality and usability of Altera's FPGA IP product portfolios.
Altera is seeking a Lead DV Engineer to focus on IP Verification & Validation in San Jose, California. The role involves developing comprehensive validation plans and collaborating with cross-functional teams to ensure robust IP functionality.
The ideal candidate has over 9 years of experience in verification processes, specifically with high-speed protocols like Ethernet/PCIe/CXL. A competitive salary range of $142.6k - $206.5k USD is offered, based on location and experience.
This role contributes significantly to enhancing the quality and usability of Altera's FPGA IP product portfolios.