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Asteralabs is seeking a Principal Design Verification Engineer in San Jose, California to lead the functional verification of high-speed SerDes/PHY IP. This role is crucial to the development of connectivity engines powering robust AI infrastructure.
The ideal candidate will possess extensive experience in design verification, with a strong emphasis on SystemVerilog and UVM methodologies, alongside a deep understanding of physical layer specifications.
A competitive salary range of $207,000 to $230,000 is offered based on experience, plus potential bonuses and incentives.
.Asteralabs is seeking a Principal Design Verification Engineer in San Jose, California to lead the functional verification of high-speed SerDes/PHY IP. This role is crucial to the development of connectivity engines powering robust AI infrastructure.
The ideal candidate will possess extensive experience in design verification, with a strong emphasis on SystemVerilog and UVM methodologies, alongside a deep understanding of physical layer specifications.
A competitive salary range of $207,000 to $230,000 is offered based on experience, plus potential bonuses and incentives.
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