Senior DRAM Digital IP Architect & Verifier

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho seeks a capable Semiconductor Design Engineer to develop competitive digital IP for advanced DRAM. The role involves defining design and verification requirements, building models, and guiding RTL and layout teams to deliver high-quality IP.

You will collaborate with CAD, modeling and verification groups, apply AI tools to improve design processes and contribute to next-generation memory technologies, with a path from architecture to verification.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 6+ years of experience in digital or semiconductor design.
• Ability to translate specifications into clear design and verification requirements.
• Strong written and verbal communication skills.
• Effective time management and prioritization skills.

Responsibilities

• Develop competitive digital IPs for advanced DRAM products.
• Define design and verification requirements from specifications and reference designs.
• Build high-level behavioral and algorithmic models for architecture verification.
• Design IP using RTL or custom methodologies and guide layout and verification teams.
• Collaborate with standards, CAD, modeling, and verification teams to improve design quality.
• Leverage AI tools to develop and improve design quality and efficiency.

Skills

Communication skills

Time management

Requirements translation

Education

B.S. in Electrical Engineering or related field

Job description

Micron Technology, Inc. in Boise, Idaho seeks a capable Semiconductor Design Engineer to develop competitive digital IP for advanced DRAM. The role involves defining design and verification requirements, building models, and guiding RTL and layout teams to deliver high-quality IP.

You will collaborate with CAD, modeling and verification groups, apply AI tools to improve design processes and contribute to next-generation memory technologies, with a path from architecture to verification.