Senior Digital IP Architect - DRAM & Verification

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Boise, Idaho seeks an experienced digital IP design engineer to develop competitive IPs for advanced DRAM products. You will translate specifications into design and verification requirements and build behavioral models to support architecture verification.

You will design IP using RTL or other methods and guide layout and verification teams, collaborating with CAD, modeling, and verification groups to improve design quality. Strong communication is essential.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field, or equivalent experience.
• 6+ years of experience in digital or semiconductor design.
• Ability to translate specifications into clear design and verification requirements.
• Strong written and verbal communication skills.
• Effective time management and prioritization skills.

Responsibilities

• Develop competitive digital IPs for advanced DRAM products.
• Define design and verification requirements from specifications and reference designs.
• Build high‑level behavioral and algorithmic models for architecture verification.
• Design IP using RTL or custom methodologies and guide layout and verification teams.
• Collaborate with standards, CAD, modeling, and verification teams to improve design quality.
• Leverage AI tools to develop, improve design quality and efficiency.

Skills

Strong communication

Time management

Requirements translation

Education

Bachelor’s degree in Electrical Engineering

Tools

RTL design

Job description

Micron Technology, Inc. in Boise, Idaho seeks an experienced digital IP design engineer to develop competitive IPs for advanced DRAM products. You will translate specifications into design and verification requirements and build behavioral models to support architecture verification.

You will design IP using RTL or other methods and guide layout and verification teams, collaborating with CAD, modeling, and verification groups to improve design quality. Strong communication is essential.