Senior IC Packaging Engineer: FEA & CPI Lead

Socket.dev; San Diego (CA); On-site; USD 127,000 - 191,000; Full time

Benefits offered by this job

Annual bonus

RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. is seeking a skilled IC Packaging Engineer to develop and apply mechanical FEA models for current and advanced packaging technologies. You will support design, NPI, CPI, and reliability teams with warpage, stress, and CPI analyses using ANSYS APDL/Workbench.

Requirements include a strong background in FEA, materials, packaging structures, and testing correlation. Collaboration across global teams and travel may be required, with Qualcomm offering a comprehensive

Qualifications

• Bachelor's degree in Chemical, Electrical, Mechanical Engineering or related field with 2+ years of experience
• Master's degree in Chemical, Electrical, Mechanical Engineering or related field with 1+ year of experience
• PhD in Chemical, Electrical, Mechanical Engineering or related field

Responsibilities

• Warpage/Stress analysis
• Solder joint reliability (SJR) prediction
• Package assembly process simulation
• Chip-package interaction (CPI) analysis
• Material characterization/testing and DOE planning

Skills

FEA expertise

Analytical skills

Project execution

Education

Bachelor's degree in engineering

Master's degree in engineering

PhD in engineering

Tools

ANSYS APDL

ANSYS Workbench

APDL macros

DOE

Job description

Qualcomm Technologies, Inc. is seeking a skilled IC Packaging Engineer to develop and apply mechanical FEA models for current and advanced packaging technologies. You will support design, NPI, CPI, and reliability teams with warpage, stress, and CPI analyses using ANSYS APDL/Workbench.

Requirements include a strong background in FEA, materials, packaging structures, and testing correlation. Collaboration across global teams and travel may be required, with Qualcomm offering a comprehensive