Staff IC Packaging Engineer - Mechanical Simulation

Qualcomm; San Diego (CA); On-site; USD 154,000 - 231,000; Full time

Job summary

Qualcomm in San Diego seeks a Senior IC Packaging FEA Engineer to develop mechanical models (ANSYS APDL/Workbench) and perform warpage and reliability analyses for next‑generation package designs. You will build robust simulations that guide design and test correlation.

You will collaborate with design, NPI and CPI teams, characterize materials, develop BKMs, and drive test correlation while supporting manufacturing and reliability goals. Occasional travel may be required.

Qualifications

• Bachelor''s degree with 4+ years of System/Package Design/Technology Engineering experience.
• Master''s degree with 3+ years of System/Package Design/Technology Engineering experience.
• PhD with 2+ years of System/Package Design/Technology Engineering experience.
• PhD preferred with 6+ years in FEA for IC packaging; 3+ years ANSYS experience; 4+ years semiconductor packaging experience.

Responsibilities

• Warpage/Stress analysis
• Solder joint reliability (SJR) prediction
• Package assembly process simulation
• Chip-package interaction (CPI) analysis
• Use advanced FEA techniques (sub-modeling, contact, nonlinear analysis)
• Material characterization/testing and DOE planning

Skills

FEA expertise

Communication skills

Project execution

Education

Bachelor''s degree in relevant engineering fields

Master''s degree in engineering

PhD in engineering

Tools

ANSYS APDL

ANSYS Workbench

DOE

Job description

Overview

This position is part of Qualcomm’s Integrated Circuits (IC) package engineering process team. This role offers a unique opportunity to impact Qualcomm’s current/future chipsets using FEA expertise, working closely with design, new product introduction (NPI) and Chip-Package Interaction (CPI) teams by providing mechanical simulation support for current HVM and advanced packaging technologies. This role requires development of mechanical FEA models (preferably using ANSYS APDL and Workbench), maintenance of APDL macros/workflows, establishment of FEA methodologies/BKM for test correlation, material characterization, and performing stress/mechanical analysis for IC package designs and failure prediction. All Qualcomm employees are expected to actively support diversity in their teams, and in the Company.

Responsibilities

Job responsibilities include but are not limited to: Warpage/Stress analysis, Solder joint reliability (SJR) prediction, package assembly process simulation, and chip package interaction (CPI) analysis. The candidate must be capable of utilizing advanced Finite Element Analysis (FEA) techniques (sub-modeling approach, contact analysis, non-linear analysis), and test procedures for material characterization/testing. Candidate should also understand the fundamentals of silicon, package, and board level interconnect technologies. The candidate is expected to have strong communications, project focus and execution skills.

Minimum Qualifications

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience.
• Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience.
• PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.

Preferred Qualifications

• Ph. D degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.
• 6+ years of combined experience in Finite Element modeling and Analysis for IC electronic package and interconnects.
• 3+ years of experience in ANSYS (APDL/Workbench).
• 4+ years of direct work experience in Semiconductor and IC microelectronic packaging industry.
• Experience with the fundamentals of IC electronic packaging structures, assembly processes, reliability testing and analysis, CPI, Package-Board interaction, and design of experiments (DOE).
• Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
• Hands-on FEA experience developing and improving BKMs for predictive modeling to guide package mechanical design and support manufacturing and reliability needs.
• Experience with material characterization/testing and developing new test methods to improve package FEA model accuracy and prediction correlation.
• Research and publications in FEA predictive modeling, Warpage, CPI, and Solder lifetime prediction (plus).
• Experience using internal AI tools to accelerate APDL coding and improve simulation workflows (plus).
• Strong analytical skills and a proven track record of project execution; excellent communication and presentation skills.
• Self-starter with high motivation and a strong commitment to product success; able to work flexible hours to support collaboration across APAC and the U.S.; occasional domestic and international travel may be required.

EEO Statement

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Compensation

Pay range: $154,000.00 - $231,000.00. This pay scale reflects the broad, minimum to maximum pay for this job code in the posted location. Salary is one component of total compensation, which also includes a competitive annual discretionary bonus program and opportunity for annual RSU grants. Additional benefits are available as part of Qualcomm’s comprehensive benefits package.