Senior IC Package Design Engineer - On-Site, High-Speed SerDes

Broadcom; San Jose (CA); On-site; USD 141,000 - 226,000; Full time

Job summary

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip BGA packages for ASICs with high-speed SerDes and high-power delivery needs. You will join a worldwide R&D team developing high-performance package designs for ASICs for AI, networking, HPC, and 5G base stations.

These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You’ll have the opportunity to collaborate to create the package structures needed to enable new design

Qualifications

• BSEE with 12+ years in flip-chip BGA package design or MSEE with 10+ years of experience.
• Knowledge of package-level signal integrity and power integrity.
• Cadence APD experience preferred; equivalent tool acceptable.
• Cooperate with a world-wide team and external vendors; strong self-management.

Responsibilities

• Overall design responsibility for ASIC package designs, including SI/PI, manufacturability, reliability, and thermal.
• Package design of critical structures for SerDes, ADC/DAC, and DDR.
• Schedule, prioritize, and track work across 2+ projects.
• General flip-chip BGA package design and engineering.
• Project management and customer interface for design projects.
• Contribute to efficiency improvements through process development, automation, and documentation.
• Physical design (layout) as a foundational responsibility.

Skills

SerDes design

Power integrity

Co-design with vendors

Self-management

Cadence Allegro

Education

BSEE or similar

MSEE or similar

Tools

Cadence Allegro APD

Cadence SKILL

Job description

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip BGA packages for ASICs with high-speed SerDes and high-power delivery needs. You will join a worldwide R&D team developing high-performance package designs for ASICs for AI, networking, HPC, and 5G base stations.

These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You’ll have the opportunity to collaborate to create the package structures needed to enable new design