Senior ASIC Package Design Manager - Lead SerDes

Broadcom Inc.; Fort Collins (CO); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Sick leave and vacation

Job summary

Broadcom Inc. seeks an experienced IC Package Design Manager to lead a team of engineers designing complex flip‑chip‑BGA packages for ASICs with high‑speed SerDes and high power delivery.

You will guide technical methodologies and project management for a worldwide R&D effort focused on AI, HPC, networking, and 5G applications. The role requires 12+ years in flip‑chip‑BGA package design, including high‑speed SerDes, and at least 3 years in management, with strong SI/PI awareness and DFx

Qualifications

• Experience leading people and projects.
• 12+ years in flip-chip-BGA package design, incl. high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity.
• Collaborate with global teams and external vendors.
• Strong self-management and organizational skills.
• Understand package design lifecycle and how substrate fits ASIC flows.
• Experience with Design for X (DFx) trade-offs and SI/PI.

Responsibilities

• Understand team members' skills to maximize productivity.
• Create and track project plans for 20+ concurrent designs.
• Organize team and customer activities to keep projects on track.
• Communicate plans, status, next steps and risks.
• Create technical methodologies for package design.
• Steer package technology and design rules with team input.
• Collaborate with customers, vendors, and cross-functional teams.

Skills

Team leadership

Project management

Cross-functional collaboration

Self-management

Education

BSEE/MSEE or similar

12+ years flip-chip-BGA package design

Job description

Broadcom Inc. seeks an experienced IC Package Design Manager to lead a team of engineers designing complex flip‑chip‑BGA packages for ASICs with high‑speed SerDes and high power delivery.

You will guide technical methodologies and project management for a worldwide R&D effort focused on AI, HPC, networking, and 5G applications. The role requires 12+ years in flip‑chip‑BGA package design, including high‑speed SerDes, and at least 3 years in management, with strong SI/PI awareness and DFx