Senior IC Layout Engineer - AR Display (Equity RSUs)

Snap; Vancouver (WA); On-site; USD 173,000 - 259,000; Full time

Benefits offered by this job

Parental leave

Medical coverage

Equity (RSUs)

Job summary

Snap Inc. is seeking a seasoned IC Layout Designer to join our AR display team. You will craft transistor-level layouts for advanced analog/mixed-signal circuits, collaborating closely with digital and analog engineers to meet area, performance, and power goals.

You will also develop scripts to automate design flows and support full-chip tape-out verification. The role requires strong Cadence Virtuoso and Calibre experience, 5+ years in layout, and knowledge of foundry rules for 22nm nodes.

Qualifications

• BSEE or equivalent experience in layout.
• 5+ years in custom layout.
• Experience with 22nm and below CMOS foundry node rules preferred.

Responsibilities

• Design Layout for AR display ICs.
• Collaborate with digital and analog engineers and layout team.
• Create reusable scripts to automate design flow and improve efficiency.
• Perform parasitic extraction and iterate design improvements.
• Prepare design documentation for internal design reviews.

Skills

Layout design

Scripting & automation

Tape-out verification

Signal integrity

Team collaboration

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Mentor Calibre

ECAD tools

Python

Job description

Snap Inc. is seeking a seasoned IC Layout Designer to join our AR display team. You will craft transistor-level layouts for advanced analog/mixed-signal circuits, collaborating closely with digital and analog engineers to meet area, performance, and power goals.

You will also develop scripts to automate design flows and support full-chip tape-out verification. The role requires strong Cadence Virtuoso and Calibre experience, 5+ years in layout, and knowledge of foundry rules for 22nm nodes.