Senior IC Layout Engineer

Insight Global; Irvine (CA); On-site; USD 110,000 - 176,000; Full time

Job summary

Insight Global in Irvine, CA is seeking an experienced Analog/RF Layout Engineer to develop custom physical layouts for high-speed semiconductor designs. You will translate schematics into DRC/LVS-clean layouts and own top-level blocks from floorplanning through tape-out, collaborating with circuit designers on power, parasitics, and routing.

The ideal candidate has extensive hands-on Cadence Virtuoso/VXL, Mentor Calibre experience, and a strong background in FinFET nodes, device matching, and

Qualifications

• 8+ years of EE experience or 6+ years with MS
• Extensive analog and high-speed layout experience (TX/RX, SerDes, PLL)
• Proficient in Cadence Virtuoso and Virtuoso VXL
• Experience with Mentor Calibre for DRC/LVS verification
• Layout for advanced FinFET process nodes
• Strong understanding of analog layout fundamentals (device matching, parasitics, power/ground architecture)
• Experience taking custom IP blocks through floorplanning, layout, verification, integration, tape-out
• Strong problem-solving and cross-functional collaboration skills

Responsibilities

• Translate analog, mixed-signal, and high-speed circuit schematics into production-ready physical layouts
• Own custom IP and top-level layouts from initial floorplanning through final tape-out and sign-off
• Perform precision device matching and critical-net routing to meet high-frequency circuit performance requirements
• Partner with circuit designers on floorplanning, power/ground architecture, layout strategy, and parasitic optimization
• Run and resolve DRC/LVS verification using Cadence and Calibre tools
• Develop layouts on advanced FinFET technology nodes while addressing complex geometry, routing, and physical-design constraints
• Support top-level integration, project scheduling, and physical-design readiness for silicon tape-out

Skills

Analog Layout

High-Speed Layout

SerDes

Cadence Virtuoso

Virtuoso VXL

Mentor Calibre

FinFET Nodes

Device Matching

Education

BS in Electrical Engineering or related field

MS in Electrical Engineering

Tools

Cadence Virtuoso

Virtuoso VXL

Mentor Calibre

Job description

Location: Irvine, CA (relocation offered)

Pay Range: $109,700 - $175,500 base + RSUs, bonuses, and benefits

Role Type: Permanent

Required Skills and Experience:

• BS in Electrical Engineering or related field with 8+ years of experience, or MS with 6+ years of related experience
• Extensive experience with custom analog and high-speed circuit layout, including TX, RX, SerDes, PLL, or similar IP
• Strong hands‑on experience with Cadence Virtuoso and Virtuoso VXL for custom IC layout
• Experience with Mentor Calibre for DRC/LVS verification and physical sign-off
• Proven layout experience with advanced FinFET process nodes
• Strong understanding of analog layout fundamentals, including device matching, critical-net routing, parasitics, and power/ground architecture
• Experience taking custom IP blocks through floorplanning, layout, verification, integration, and tape‑out
• Strong problem‑solving and cross-functional collaboration skills

Key Responsibilities:

• Translate analog, mixed‑signal, and high‑speed circuit schematics into production‑ready physical layouts
• Own custom IP and top‑level layouts from initial floorplanning through final tape‑out and sign‑off
• Perform precision device matching and critical‑net routing to meet high‑frequency circuit performance requirements
• Partner with circuit designers on floorplanning, power/ground architecture, layout strategy, and parasitic optimization
• Run and resolve DRC/LVS verification using Cadence and Calibre tools
• Develop layouts on advanced FinFET technology nodes while addressing complex geometry, routing, and physical‑design constraints
• Support top‑level integration, project scheduling, and physical‑design readiness for silicon tape‑out

Job Description

We are seeking an experienced Analog/RF Layout Engineer to develop custom physical layouts for high‑speed analog and mixed‑signal semiconductor designs. This engineer will translate circuit schematics into DRC/LVS‑clean layouts while partnering closely with circuit designers on floorplanning, device matching, critical‑net routing, power architecture, and parasitic optimization. The role will own custom IP and top‑level blocks from initial floorplanning through verification, integration, and tape‑out. The ideal candidate has extensive experience with high‑speed circuits such as TX, RX, SerDes, and PLL designs. Strong hands‑on expertise with Cadence Virtuoso, Virtuoso VXL, Mentor Calibre, and advanced FinFET process nodes is required.